TMS320C6655 Looback Mode

James Jolliffe

We are using PCIe link between FPGA and 6655 DSP. We are currently having some trouble getting link up on our custom board and are trying to get Ibert serial analyzer within Xilinx Chip Scope tool up and running. We are able to have Ibert running on near end within GTP core of FPGA but when we try to enable far end DSP device in loopback mode it is not working. We would like to know the exact steps to properly put the DSP into lookback mode so that we can analyze our PCIe link using Xilinx Ibert tool in far end mode...

Thanks,

James

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

I have tested PCIe PHY loopback on C6678 EVM board. the same initialization steps are enough for C6655 device. Please take a look at below e2e link.

Thanks,

0 James Jolliffe over 10 years ago in reply to Ganapathi Dhandapani95

Intellectual 960 points

I reviewed section 2.12.2 Phy Looback in Keystone PCIe Document. Currently we are not getting past PCIe link training. One of the last comments in PCIe spec is to insure link training completion. Is it not possible to get loopback mode working without getting past link training?

James

0 Ganapathi Dhandapani95 over 10 years ago in reply to James Jolliffe

TI__Mastermind 28085 points

Hi,

Link training is required for PCIe loopback mode testing. I have posted tested PCIe loopbak code in below e2e link, refer this code for your testing. (2086.pcie_sample.txt)
e2e.ti.com/.../1244423

Thanks,

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TMS320C6655 Looback Mode