the number of cycle CPU changes for the same function : DSP C6678

ZAKARIA BOURZOUK

hello,

every time I execute my program in CCS, I find a number of CPU cycle different for the same function, and I do not know which of these values take.

I do not know if it's because of the target, or maybe I have to turn off before I launch a second execution or what !!

I would like an explanation or solution for this problem.

Thanks,

Zakaria.

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

For my understanding, you run the same test application on two target boards and get different CPU cycle value. Is it correct?

Have you using EVM or custom board for your testing? What is the input clock frequency?

Thanks,

0 ZAKARIA BOURZOUK over 10 years ago in reply to Ganapathi Dhandapani95

Intellectual 560 points

No, I run the test for the first time and I get the number of cycles, then I rerun the same test for the second time and I get a different number of cycle, this is in the same target.
I use TMDXEVM6678L Development Kit . Clock frequency is 1 GHz .
Thanks,

Zakaria

0 Ganapathi Dhandapani95 over 10 years ago in reply to ZAKARIA BOURZOUK

TI__Mastermind 28085 points

Hi,

Have you using TI provide GEL file for initializing the EVM board? Share your test code I will try to reproduce your issue.

Thanks,

0 ZAKARIA BOURZOUK over 10 years ago in reply to Ganapathi Dhandapani95

Intellectual 560 points

No , I do not use it.
here is the test :

/***************************************************\
Nbefore_RC=CSL_tscRead ();
//PCIe transfer using CPU
for (i=0; i<pcie_SIZE/4; i++)
{
*((volatile UINT32 *)dst_data + i) = src_data[i];
}

Nafter_RC=CSL_tscRead ();
Ncycle_RC=Nafter_RC-Nbefore_RC;
/***************************************************\

Thanks,

Zakaria

0 Chad Courtney over 10 years ago in reply to ZAKARIA BOURZOUK

TI__Mastermind 30825 points

Zakaria,

The first time you run something, you're likely caching the code into L1P cache space and it takes a bit longer. Also, if you doing memory accesses, it's probably caching the data into L1D memory and that takes more cycles. The second time if the program data is resident in cache it's going to be quicker and more of a steady state from that point on if you're re-running the same code.

Generally the 'cached' version of the 2nd run is what's taken for typical performance numbers, as that's what's typically ran on kernels that are constantly used. But some control code that may only be use infrequently that has usually been evicted from cache in-between runs, would probably want the first (uncached) version.

Best Regards,

Chad

0 ZAKARIA BOURZOUK over 10 years ago in reply to Chad Courtney

Intellectual 560 points

thank you so much for the information that you have give me.

Thanks,

Zakaria

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the number of cycle CPU changes for the same function : DSP C6678