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66AK2H12 internal pattern length into the K2H package

RY9983
Guru 10570 points
Other Parts Discussed in Thread: 66AK2H12

Hello,

I have encountered DDR3 read trouble in our system of 66AK2H12.
I have a question about:

- Do I have to concern internal pattern length into the K2H package for pcb design?

- If yes, can you provide pattern length information as following?:
DDR3A
DDR3B
SRIO
USB3.0
PCIe

Best regards, RY

  • 0
    TI__Mastermind 42545 points
    Hi RY,
    The lengths of the internal traces on the sub-strait are factored into the routing guidelines for the part. We do not provide the internal routing lengths for these signals. If you meet the routing guidelines for the PCB, you should be successful.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    Guru 10570 points
    Bill-san,
    Thanks for your reply.

    Can you provide internal trace latency of DDR3 into the package?

    In our system, 16 DDR3 memory devices are implemented in our board.
    We need to know difference of the latency to advance debugging including accurate skew control.

    Best regards, RY
  • 0 in reply to RY9983
    Guru 10570 points

    Could you provide your return?

    Best regards, RY

  • 0 in reply to RY9983
    TI__Mastermind 46460 points

    RY,

    As Bill has already stated, the routing skew within the dia and package is already comprehended within our timing budgets.  This delay skew is also very small (less than 3ps and 15 mils).  If you are having difficulty with your layout, you need to verify that you ghave followed the board routing rules provided and that you have properly configured the PHY and SDRAMs.  Please refer to the DDR3 Layout Guidelines (SPRABI1), DDR3 Controller UG (SPRUHN7) and the K2 DDR3 Init App Note (SPRABX7).

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Guru 10570 points

    Tom-san,

    Great thanks!  Your information is very useful.
    I understand that delay skew is less than 3ps, it's almost match. Thanks.

    Best regards, RY