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mcbsp + edma3 event missed

Ganz
Intellectual 770 points

Hi,

I have a application that need to send data across mcbsp (fifo enabled) in 7 byte packet.

Option1: Using EDMA A-syncgronized transfer

ACNT = 1, BCNT = 1, CCNT = 7

It requires 7 XEVT(XRDY) for the transfer. This option works fine when the system is not busy. The 56 bits of data transfer completes in 56 clock ticks.  But when the system is busy, occasionally there is a gap inside the data pack, it needs 64 clock ticks to complete the 56 bits of data transfer, looks like the EDMA3 loses the bus to other master.

Option2: Using EDMA AB-syncgronized transfer

ACNT = 1, BCNT = 7, CCNT = 1

With this option, even the system is busy the 7 byte packed data transfer can always complete in 56 clock ticks as expected. But I will get a  edma3 event  missed error because it's expecting one XEVT only. I need to bypass the edma3 event  missed detection for it to work.

Any suggection how to make option1 work in busy system or how to make option 2 work  with event  missed detection  enabled so that it can detect ture event missed error.

DSP: C6655

mcBsp registers:

DRR = 0x00000000

DXR = 0x00000030

SPCR = 0x00400000

RCR = 0x00010000

XCR = 0x00050600

SRGR = 0x20800108

MCR = 0x00000000

RCERE0 = 0x00000000

XCERE0 = 0x00000000

PCR = 0x00000a00

RCERE1 = 0x00000000

XCERE1 = 0x00000000

RCERE2 = 0x00000000

XCERE2 = 0x00000000

RCERE3 = 0x00000000

XCERE3 = 0x00000000

WFIFOCTL = 0x00010101

WFIFOSTS = 0x00000000

RFIFOCTL = 0x00010101

RFIFOSTS = 0x00000000

Ganz

  • 0
    TI__Mastermind 35645 points

    Hi Ganz,

    Thanks for your post.

    With reference to Option2, please ensure the Write FIFO has sufficient space in order to avoid the edma3 event  missed error. It is obvious in your case which misses the transmit DMA event to the DMA controller (XEVT) due to insufficent space in the Write FIFO. May be, you could disable the Write FIFO at the desired instance through setting WENA bit of WFIFOCTL register so that, the Write FIFO status register (WFIFOSTS) would reset to 0 and the pointers are initialized which would flush the Write FIFO & enable the Write FIFO later. This would create enough space for WNUMEVT words of data, then an XEVT would be generated to the DMA controller which wouldn't miss the DMA Tx. event.

    Also, Please check the status of Write FIFO register through Write level (WLVL bit) of WFIFOSTS and ensure the number of words currently in the Write FIFO at the particular instance where you miss the XEVT.  Kindly refer sections 3.13 & 3.14 for more info on WFIFOCTL & WFIFOSTS from the keystone mcbsp user guide as below:

    http://www.ti.com/lit/ug/spruhh0/spruhh0.pdf

    Thanks & regards,

    Sivaraj K

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