DM647/8 and CLKDIV4 0 domain (for example, EMIFA)

Hi Yury,

Please refer to the data sheet of DM647, chapter 6.4 and 6.4.1

www.ti.com/.../tms320dm647.pdf

SYSCLK4 is used as the EMIFA AECLKOUT
[When SYSCLK4 is used as the EMIF input clock source, the actual clock goes through a divider and
the frequency would be SYSCLK4 divide-by-2 (see Figure 6-5, PLL Input Clock).]

The PLL multiplier controller (PLLM) must be programmed after reset. There is no hardware CLKMODE
selection on the device. Since the divider ratio bits for dividers D1, D3, D5, and D6 are fixed, the
frequency of SYSCLK1, SYCLK3, SYSCLK5, and SYSCLK6 is tied to the frequency of SYSREFCLK.
However, the frequency of SYSCLK2 and SYSCLK4 depends on the configuration of dividers D2 and D4.
For example, with PLLM in the PLL1 multiply control register set to 10011b (x20 mode) and a 35-MHz
CLKIN1 input, the PLL output PLLOUT is set to 700 MHz and SYSCLK1 and SYSCLK3 run at 233 MHz
and 117 MHz, respectively. Divider D4 can be programmed through the PLLDIV4 register to divide
SYSREFCLK by 8 (2 * (PLLDIV4.RATIO+1)) such that SYSCLK4 runs at 87.5 MHz.



Yes, you can configure the CLKDIV (PLLDIV4.RATIO) to 4,5,6,7,8 but it will get divided further by 2.

Say e.g,

(2 * (PLLDIV4.RATIO+1))

If you want to operate EMIFA 75MHz and DSP at 900MHz then
900MHz/75MHz = 12
PLLDIV4.RATIO = 5 and default divider will be 2 so
total (5+1)*2) = 12

So, you have to set PLLDIV4.RATIO to 5 and DSP should operate at 900MHz.

I would like to suggest to use gel file for clock modification and experiment.

C:\ti\ccsv5\ccs_base\emulation\boards\evmdm648\gel\EVMDM648.gel

1) Try to change DIV4 and probe the EMIFA clock.

div2 = (*pll_div2 & 0x1f) +1;
div4 = (*pll_div4 & 0x1f) +1;

// Print freq info...
GEL_TextOut( "PLL1 Setup for DSP @ %d MHz, SYSCLK2 = %f MHz, SYSCLK4 = %f MHz.\n",,,,, dsp_freq, ((float)(dsp_freq)/div2), ((float)(dsp_freq)/div4));
GEL_TextOut( "PLL1 Setup... Done.\n" );


2) Also try to change the "PLLDIV4.RATIO" to change the SYSCLK4.