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SPI2_ Clock issue in TI811x



HI,

In ti811x i have a problem where im trying to communicate with the DSP of other hardware, but seems i have interference

there is 4 lines thar are for SPI2 comunication, when trying to put them as input (gpio[1]15, gpio[1]16, gpio1[17], gpio1[18]), for some unknown reason;

  • SPI2_SCLK is still low when we try to pull high, even setting it in console (echo 1 > sys/class/gpio/gpio50/value)
  • the pincntl for this is PINCNTL112 /0x4814 09BC and seems to be pinmux with GPMC functionallities
  • we also put  PSI2_SCS PINCNTL125 / 0x4814 09F0 as input and all the other spi2 related pins

what we try to do is held that dsp hardware on reset PINCNTL113 /0x4814 09C0 (as output low) and putting all the spi2 pins as inputs to not interfere, but they still interfere. Can somebody help me with this?


Thanks

  • Hi Alfred,

    You are using TI811x (J5Eco) custom board (not TI EVM), right?

    From what I understand you are connecting TI811x McSPI2 to external device/DSP? Or TI811x GPIO to external device/DSP? Which physical pins exactly you are connecting to the external device/DSP?

    Regards,
    Pavel
  • Hi Pavel,

    As far as i know, we are not using McSPI2, i've been told they are other set of lines that we are not using,
    Our device is already communicating correctly, the problem we have is that when we hold it in reset with the pin PINCNTL113 /0x481409C0 (set low) something happen that make the SPI2_SCLK PINCNTL229 /0x4814 0B90 to interfere with our device comunications.

    This is not about conecting the DSP device with SPI2, is about we want to set the SPI2 in a state that doesnt interfere(input high?), we tested physically cutting spi2_sclk line , and our device works properly, we want to pur spi2_sclock as an input high to not interfere in any way with our already functional hardware,

    So as a resume, when we set PINCNTL113 /0x481409C0 (low), SPI2_SCLK PINCNTL229 /0x4814 0B90 (that is low) can't be set high. We are looking for something that forcefully set that spi2_clk low (by rewritting our changes).

    Those pins are related to the GPMC, what i'm trying to do now is remove NOR flash init to see if that works.

    Thanks a lot in Advance Pavel. I hope this helps
  • Regarding pin input and pin behaviour on reset see:

    TRM, 3.2.58 PINCNTL1 to PINCNTL270 Register
    [18] RXACTIVE = 1 Receiver Enabled

    Datasheet, 7.3.18 Pin Behaviors at Reset
  • Alfred,

    What is your boot mode?

    Note that ROM Code makes some changes in pinmux registers. See TRM, chapter 5 ROM Bootloader.

    For example in SPI boot mode see section 5.6.5.4 Pins Used

    Regards,
    Pavel
  • See also if the below lines of code in the linux kernel are overwriting your PINCNTL229/0x48140B90 settings:

    <linux kernel>/arch/arm/mach-omap2/devices.c

    static void __init ti81xx_video_mux(void)
    {
    else if (cpu_is_ti811x()){

    omap_writel(0x1, 0x48140b90);

    omap_writel(0x1, 0x48140B90);

    }

    static void ti814x_nor_init(void)
    {

    omap_mux_init_signal("vout1_r_cr3.gpmc_a_14_mux1", TI814X_PULL_UP);
    }

    BR
    Pavel
  • I boot from an SD card, i guess is MMC/SD
  • Thanks a lot, let me check those lines, they look like what i was looking for
  • Hello Alfred,

    In addition, I suggest you to check if your McSPI2 module is functional. Check CM_ALWON_SPI_CLKCTRL register it manages the SPI0, SPI1, SPI2 and SPI3 clocks.

    Best regards,
    Yanko
  • Alfred,

    If you don't use McSPI module, please check if your GPIO modules are enabled:
    CM_ALWON_GPIO_0_CLKCTRL This register manages the GPIO_0 clocks
    CM_ALWON_GPIO_1_CLKCTRL This register manages the GPIO_1, GPIO_2, GPIO_3, GPIO_4, and GPIO_5 clocks.

    Best regards,
    Yanko
  • Pavel and Yanko,

    Thanks for your help, but because of time it was decided to take another route to fix, i will test this later.

    What i could see before that was, from Pavel Response:

    static void ti814x_nor_init(void)
    {
    omap_mux_init_signal("vout1_r_cr3.gpmc_a_14_mux1", TI814X_PULL_UP);
    }

    //thas was the problem with the spi2_sclock, still i will test it in a few hours and mark as answered if that was

    From Yanko response:

    CM_ALWON_GPIO_0_CLKCTRL
    CM_ALWON_GPIO_1_CLKCTRL
    were set properly in the uboot
  • Hey Pavel,

    My core issue was not fixed with this, but the SPI2_SCLK was getting overwritten by that, so this would be the answer for my specific question.

    Just to clarify, the fix suggested by Yanko:
    CM_ALWON_GPIO_0_CLKCTRL
    CM_ALWON_GPIO_1_CLKCTRL
    This are set correctly, so they were not the issue, still the are completely necessary to run the GPIO banks so this should be the first one i check if i have an issue like GPIO not responding etc (this note is for documentation purpose).

    Thanks a lot Pavel, Yanko