SPI Word Length with a ICE V2 and os_drv library

Konstantin Klein

Hello,

We have implemented an SPI1 interface for the ICE v2 through the os_drv library. Now we are facing the problem, that the max WordLenght is limited to 32bit in mcspi.c.

Is there any possibility to enlarge the transmission cycle to 40 or more bits(variable)? We need to transmit 40 till 64 bit in one cycle, what means to have up to 64 bit in the clock and low level CS without any interruptions!

How to change the function McSPIWordLengthSet then?

void McSPIWordLengthSet(unsigned int baseAdd, unsigned int wordLength, unsigned int chNum)
{
   /*Clearing the wordLength field of MCSPI_CHCONF register.*/
   HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~MCSPI_CH0CONF_WL;
   /* Setting the wordlength field. */
   HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (wordLength & MCSPI_CH0CONF_WL);
}

Thank you in advance for your support!

Kind regards,

Konstantin

over 10 years ago

0 Vinesh Balan over 10 years ago

TI__Expert 7360 points

Konstantin,

As per the AM335x TRM, SPI Word length is configurable only from 4 to 32 bit.

Regards,
Vinesh

0 Konstantin Klein over 10 years ago in reply to Vinesh Balan

Prodigy 70 points

Dear Vinesh,

thank you for your response. i am aware of the TRM content. The question is, is there a possibility to keep CS low between the transmissions of the words on the SPI bus? Or more precise, By using the command void McSPICycle(int spiId, unsigned char *buf, unsigned short len, unsigned int chNum) you are able to indicate the length of tranmission (how many words). But between the transmissions of these words, am 3359 sets the CS to high for a short moment (attached picture).

TRM is mentioning that it is possible to keep SPIEN in Active Mode (chapter 24.2.3.1.2 on page 4784). But how to do it programmatically? I assume that McSPICSAssert() and DeAssert would make that job, but it dous not work. I am using the starterware snippet:

char McSPIRWLongChar( int spiId, unsigned long buf,
                unsigned long len, unsigned short spiCs )
{
    unsigned int i;
    volatile int loop;

    int baseAdd = SOC_SPI_1_REGS;
    McSPIChannelEnable(baseAdd,chNum);
    /* SPI System Register Configuration*/
    HWREG(baseAdd + MCSPI_SYST) = (HWREG(baseAdd + MCSPI_SYST) &
                                    ~MCSPI_SYST_SPIEN_1);

    McSPICSEnable(baseAdd);
    McSPICSAssert(baseAdd, chNum);
    unsigned char result;
    for ( i = 0 ; i < len ; i++ )
    {
        loop = 1000;
        while(((McSPIChannelStatusGet(baseAdd,chNum) & MCSPI_CH_STAT_TXS_EMPTY) == 0) && (loop--));
        if(loop == 0)
            return;
        McSPITransmitData(baseAdd,buf,chNum);
        loop = 1000;
        while(((McSPIChannelStatusGet(baseAdd,chNum) & MCSPI_CH_STAT_RXS_FULL) == 0) && (loop--));
        if(loop == 0)
            return;
        result = (unsigned char)McSPIReceiveData(baseAdd,chNum);
    }

    McSPICSDeAssert(baseAdd,chNum);

    HWREG(baseAdd + MCSPI_SYST) |= (1 << MCSPI_SYST_SPIEN_0_SHIFT);

    McSPIChannelDisable(baseAdd,chNum);

    for(loop = 0; loop < 1000; loop++);
    return result;
}

CS is selected to LOW. We are using single channel as expected in TRM.

Regards,
Konstantin

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SPI Word Length with a ICE V2 and os_drv library