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OMAP-L137 RMII clock

Vigliarolo
Prodigy 20 points
Other Parts Discussed in Thread: OMAP-L137, DP83848YB

In my design I plan to source the RMII clock from the OMAP to the PHY (SYSCLK7) as explained in the OMAP-L137 Applications Processor System Reference Guide.
In revision C of this manual (SPRUG84C March 2010) at chapter 7.3.4 there is this note:
"The SYSCLK7 output clock does not meet the RMII reference clock specification of 50MHz +/-50ppm." This note was not present in revision B (SPRUG84B).
I know that a PLL, once locked, cannot change the ratio beetwen the input and output frequency; the only thing it can do is to modify the jitter (depending on its bandwith, noise, etc.).

I  will use the DP83848YB that is quite tolerant to jitter (if interested you can see "PHYTER 100 Base-TX Reference Clock Jitter
Tolerance" at http://www.national.com/an/AN/AN-1548.pdf)
 
My questions are:

1) Why was the note added in rev. C ?
2) What are the settings of the OMAP PLL (division ratios and input frequency) that minimize the output jitter (I will operate he chip at 300MHz)?
3) How much jitter can I expect when sourcing the RMII clock from SYSCLK7?
 
Thank you!

 

 

 

  • 0
    TI__Guru 62975 points

    Vigliarolo,

    The note was added to the reference guide because there is an official RMII spec for jitter and we are unable to guarantee that the PLL output clock will meet the jitter requirement.  While the jitter on the L137 PLL has not been characterized, we believe that the jitter can be about 2.5% of the output frequency.  Again, this number is not characterized, verified, or guaranteed so it could be better or worse.

    -Tommy

  • 0 in reply to tlee
    Prodigy 20 points

     Hi Tommy!

    The RMII specification is available at: http://www.national.com/appinfo/networks/files/rmii_1_2.pdf and, as you can see, there is no reference to jitter.

    Usually a phy connected by rmii don't use an internal pll to transmit data but use directly the rmii clock. So the problem becomes the jitter specification of ieee 802.3 that, for 100baseTX, allows for a maximum jitter of 1.4 ns on transmitted data (by reference to ANSI X3.263). If interested you can see: ftp://ftp.iol.unh.edu/pub/ethernet/test_suites/CL25_PMD/PMD_Test_Suite_v3.4.pdf

    The phy I plan to use (DP83848YB) guarantees this parameter (T2.8.2) if the rmii clock has a jitter less than 800 ps (Table 8) but typically can live with up to 1.2 ns of rmii clock jitter. This level of jitter is quite high.

    You say that ”While the jitter on the L137 PLL has not been characterized, we believe that the jitter can be about 2.5% of the output frequency”. The jitter is, obviously, measured in seconds so, if I interpret “2.5% of the output frequency” as 2.5% of the output frequency period, I end up with 500ps and I can live with it.

    But you say “Again, this number is not characterized, verified, or guaranteed so it could be better or worse.”

    I cannot believe that a a reputable manufacturer like TI produce a component with a PLL inside without characterizing its jitter. So I ask you to contact someone in your organization to have at least a typical number to share with me and with the other users of the L137.

    I know that I am annoying you but, please, understand that having an answer is very important for my project.

    Finally I think that you should remove any reference to frequency in the added note replacing it with a reference mentioning the typical jitter you can expect from RMII_MHZ_50_CLK when it is driven by CLKOUT7.

    Regards,

    Roberto

    P.S.

    CLOCKOUT7 is obtained by division of a system frequency and I think that, unless there is huge noise in the chip, the jitter of CLOCKOUT7 is similar to the jitter in the 300MHz frequency (3.3 ns period). You can understand that if the jitter in a 3.3 ns period is as high as 1.4 ns the L137 would have big problems :-)

  • 0 in reply to Vigliarolo
    TI__Guru 62975 points

    Roberto,

    I'm working off the assumption that the 50MHz +/- 50ppm spec for the reference clock in chapter 5.1 is "jitter" like.  I think you can assume that typical jitter would be 2.5% of the output period from the PLL, and the ppm jitter may be reduced some by the post-divider stages.

    -Tommy