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OMAP GPMC module problem with the multiplex address/databus under a single write

Other Parts Discussed in Thread: OMAP3530

Hello

Im using a OMAP3530 processor and I want to make a write process to external memory on a FPGA. I have setup my system so all the control signal(Chip Select,Adress Valid and Write Enable) have the correct timming. The problem is the multiplexed address/data bus, it change from address to data before the Address Valid have deasserted? Any have some idea. I have a chipscope picture from the FPGA view below. Any ideas would help a lot