This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Sys/Bios APIs for external memory protection

Other Parts Discussed in Thread: SYSBIOS

Hi,
I am trying to implement the memory protection feature in C6678. While I can find both Sys/Bios and CSL APIs for protection of L1P/L1D/L2Cache, I cannot find the Sys/Bios APIs for protection of shared MSM and DDR memory. Are there some Sys/Bios APIs for protection of MSM/DDR( or more precisely for managing XMC registers)? or CSL APIs are the only way to configure the memory protection registers in the XMC?

Also in case of XMC registers, is there some default mechanism also that sets the memory segments and their accesses in MSM/DDR? or do I have to create segments myself and set their accesses?

Regards

Nikhil

  • Hi Nikhil,
    I am not aware of SYS/BIOS API for memory protection but have seen some example project with Keystone workshop manual.
    I am checking to locate the example project with our team and get back to you if got any information.

    In the meantime you can also check in TI-RTOS forum for SYS/BIOS API availability for memory protection. Thank you.
  • Hi Nikhil,

    I am not expert on SYS/BIOS, you can post your question in TI-RTOS forum to confirm the SYS/BIOS API availability for memory protection.

    Take a look at attached CSL API based XMC example code for DDR memory.

    
    
    #include <c6x.h>
    #include "stdio.h"
    #include <stdlib.h>
    
    #include <xdc/std.h>
    #include <string.h>
    
    /*  -----------------------------------XDC.RUNTIME module Headers    */
    #include <xdc/runtime/System.h>
    #include <xdc/runtime/IHeap.h>
    
    /*  ----------------------------------- IPC module Headers           */
    #include <ti/ipc/Ipc.h>
    #include <ti/ipc/MessageQ.h>
    #include <ti/ipc/HeapBufMP.h>
    #include <ti/ipc/MultiProc.h>
    
    /*  ----------------------------------- BIOS6 module Headers         */
    #include <ti/sysbios/BIOS.h>
    #include <ti/sysbios/knl/Task.h>
    
    /*  ----------------------------------- To get globals from .cfg Header */
    #include <xdc/cfg/global.h>
    
    
    
    #include <ti\csl\csl_cache.h>
    #include <ti\csl\csl_cacheAux.h>
    #include <ti\csl\csl_chip.h>
    #include <ti\csl\csl_chipAux.h>
    #include <ti\csl\csl_xmc.h>
    #include <ti\csl\csl_xmcAux.h>
    #include <ti/csl/soc.h>
    #include <ti/csl/csl.h>
    #include <ti/csl/cslr_xmc.h>
    
    #include <ti/ipc/Ipc.h>
    #include <ti/ipc/MessageQ.h>
    #include <ti/ipc/HeapBufMP.h>
    #include <ti/ipc/MultiProc.h>
    
    
    
    #pragma DATA_ALIGN(myBuffer, 8);
    #pragma DATA_SECTION(myBuffer, ".DDR_private");
    volatile unsigned int myBuffer[1024];
    
    
    void     fillMemory(unsigned int *baseAddress, unsigned int startValue, int numberOfValues)
    {
    	int   i    ;
    	unsigned int *p    ;
    	p = baseAddress   ;
    	for (i=0; i<numberOfValues;i++)
    	{
    		*p++ = startValue    ;
    		startValue = startValue + 1  ;
    	}
    }
    
    
    void  erasememory(unsigned int *baseAddress,  int numberOfValues)
    {
    	int   i    ;
    	unsigned int *p    ;
    	p = baseAddress   ;
    	for (i=0; i<numberOfValues;i++)
    	{
    		*p++ = 0xFACEBAD  ;
    
    	}
    }
    
    
    
    void main()
    {
    	int coreNum   ;
    	Uint32 index;
    	CSL_XMC_XMPAXH mpaxh;
        CSL_XMC_XMPAXL mpaxl;
        int  i   ;
        unsigned int startValue   ;
        unsigned int *baseAddress   ;
        int numberOfValues    ;
        volatile uint32_t* lvMarPtr;
        unsigned int L_Value, H_Value   ;
        unsigned int xx    ;
    
    //    Ipc_start();
    
    
    ////    First step, configure the MPAX registers
    ////    We will use register number 4
    
    	coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
    //	printMPAXRegisters()  ;
    
    //   To load the H part of the register, we use the function        CSL_XMC_setXMPAXH (index, &mpaxh);
    	ranDelay(coreNum * 10)  ;
    	   printMPAXOneRegisters(4)  ;
    	   
    //      Here comes CSL configuration  - we use CSL functions to configure the MPAX	   
    	   
    #if  1
         index = 4    ;
         mpaxh.segSize   =  23  ; //  Each segment is
         mpaxh.bAddr = 0x90000;   //    base address
    
         CSL_XMC_setXMPAXH (index, &mpaxh);
    //
    //   For the lower part,
    
    
    
    
         mpaxl.ux = 1;
         mpaxl.uw = 1;
         mpaxl.ur = 1;
         mpaxl.sx = 1;
         mpaxl.sw = 1;
         mpaxl.sr = 1;
    
         xx = (0x810 + coreNum * 0x01) << 12 ;
         printValueUnsigned (xx)  ;
         mpaxl.rAddr = xx    ;
    
    
         CSL_XMC_setXMPAXL (index, &mpaxl);
     	//printMPAXRegisters()  ;
        printMPAXOneRegisters(4)  ;
    ///   Disable the Cache
    ///   The MAR registers for logical address 0x9000 0000 to 0x9fff ffff is 144 to 159
    #endif
    
    
    //      Here comes direct configuration  - we use direct access to the Memory mapped Register configure the MPAX	
    
    #if  1
         lvMarPtr = (volatile uint32_t*)0x08000020;
    
         H_Value = 0x90000017    ;
    
         if (coreNum == 0) L_Value = 0x8100003f    ;
         if (coreNum == 1) L_Value = 0x8110003f    ;
         if (coreNum == 2) L_Value = 0x8120003f    ;
         if (coreNum == 3) L_Value = 0x8130003f    ;
         if (coreNum == 4) L_Value = 0x8140003f    ;
         if (coreNum == 5) L_Value = 0x8150003f    ;
         if (coreNum == 6) L_Value = 0x8160003f    ;
         if (coreNum == 7) L_Value = 0x8170003f    ;
    
    
         *lvMarPtr++ = L_Value;
         *lvMarPtr++ = H_Value;
    
         printMPAXOneRegisters(4)  ;
    
    
    #endif
        for (i=144; i<160; i++)
        {
           CACHE_disableCaching  ( (unsigned char) i )   ;
           CACHE_getMemRegionInfo(i,0,0)   ;    //  this if for pre-fetch
        }
    
        startValue = (0x2 * coreNum  )  <<  16     ;
    
        baseAddress = (unsigned int *) &myBuffer[0]  ;  //     0x90000000    ;
        numberOfValues = 10   ;
    
        erasememory(baseAddress, numberOfValues )   ;
        fillMemory(baseAddress, startValue, numberOfValues)    ;
    
        printDone(coreNum)  ;
        stay()    ;
    }
    
    
     For more information refer chapter 7 "Using MPAX to Define Private Core Memory in DDR" on Keystone Lab Manual.
    www.ti.com.cn/.../sprp820.pdf

    Also refer the below thread.
    e2e.ti.com/.../853734

    Thanks,

  • Hello,

    We are working on TCI6670 evm.

    We are using SYSBIOS APIs to enable memory protection at L2SRAM of a core.
    But we are not able to enable CorePac interrupt controller input event 124 to trigger exception for DSP core L2 violation. We get an exception(system crashes) just after the function call Exception_evtExpMaskEnable(124)

    While debugging this issue,it's been seen that-
    If we just comment out sysbios api-  Ipc_start() function call(Ipc_start already exists in our software to perform IPC among 4 cores), we are able to successfully enable this input event 124. And when we can set the desired memory attributes further and successfully get an exception in case of any memory violation at L2

    So, is there any dependency or relation between Exception_evtExpMaskEnable and Ipc_start functionality?
    I mean is this 124 event used by Ipc_start?
    Please find below the code sequence that is executed.

    In static configuration file, we have invoked -
    -------------------------------------------------------------------------------------------------------------------------

    var Exception = xdc.useModule('ti.sysbios.family.c64p.Exception');
    Exception.exceptionHook = "&exceptionHandler";
    Exception.enableExternalMPC = true;
    var memProtect = xdc.useModule("ti.sysbios.family.c64p.MemoryProtect");

    Pseudocode-
    exceptionHandler
    {
    /*required handling*/
    }

    main()
    {
    Ipc_start();
    Exception_evtExpMaskEnable(124) /*To trigger an exception by routing DSP core L2 violation to CorePac interrupt controller input event 124 */
    MemoryProtect_setPA((Ptr)0x12800000, 0x20000, 0x109);  /* To set 128K L2SRAM of core 2 at execute-mode(for both user and supervisor mode)*/
    }
    -----------------------------------------------------------------------------------------------------------------------------

    So, while putting breakpoints and commenting MemoryProtect_setPA for a run, we have observed in dissassembly that-
    a. If  Ipc_start is not commented, Exception_evtExpMaskEnable(124) will itself throw an exception,i.e,when we write or enable 124th event,exceptionHandler gets invoked.
    b. But,if  Ipc_start is commented,  Exception_evtExpMaskEnable(124) will set 124 event successfully and code flow works properly

    Please guide us in this issue .
    Thanks
    Jeanne

  • Hi,

    SYS/BIOS based CorePac's interrupt example is available in below wiki link, refer this code to implement the corepac interrupt on your test code.
    processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices

    Thanks,
  • Hello,

    Please guide us in this problem.

    Please let me know if something is unclarified

    Regards,

    Jeanne