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OMAP-L137 ePWM sync questions

clam
Expert 8785 points

Below are some good questions about ePWMs synchronization

- Christina

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Question: However, my understanding is that SyncOut can be programmed to send a pulse out only when the ePWMx counter is ZERO or CMPB. Is this correct?
Answer: This is correct.

Question: I think it would have been much better if the SyncOut pulse can also be set when counter equals PRD. We could then use the SyncOut from the last module to trigger external ADC start of conversion without CPU intervention.
Answer: There are a few options
-        If they are not using CMPB, they can set CMPB to equal PRD and trigger on CMPB.
-        If up-down count can be changed to up count or down count, then PRD will equal ZERO.
-        Instead of using hardware triggered sync on ZERO or CMPB, they can use software interrupts.  When a CTR=PRD interrupt occurs, the software can force a syncout pulse by setting TBCTL[SWFSYNC].  This will cause more overhead though. 

Question: Also how do you set the width of the SyncOut pulse? Is it fixed? or programmable?
Answer: This width is fixed.  The timings are available in the datasheet.

Question: How do we do double updates in this scheme where the SyncOut pulse is only generated on the valleys or when counter reaches ZERO? Do we have to set a GPIO from ePWM_INT event and use external glue logic to OR this signal with SyncOut pulse? Assuming SyncOut pulse is set when counter reaches ZERO.
Answer: TBCTL[SWFSYNC] is the only signal internally ORed with the syncout pulse.  

Question: It would have been nice to allow a programmable delay on the ePWM event interrupt? This would have allowed triggering of slower ADC converters on peaks and valleys and create a CPU interrupt when the conversion is complete.
Answer: No programmable delay on the ePWM event interrupt.

Question: I noticed in the user guide that it is possible to connect the SyncOut pulse from the last ePWM unit to the eCAP1 unit. Where do I find details? It is a nice feature and will be very helpful to us.
Answer: ECAP1 is a typo in the userguide.  It should say ECAP0.  The syncout from EPWM2 is internally connected to the ECAP0 syncin.  As long as both EPWM2 and ECAP0 modules are configured correctly to use sync input/output, no additional configuration is needed.

  • TI__Guru 62975 points

    Good to know.  Thanks!

  • TI__Expert 4745 points

    Thank you Christina,

    just to clarify ...to generate complementary outputs, do we have to use CMPB?

  • in reply to DaveB123
    TI__Expert 8785 points

    Hi Dave,

    If possible, can you provide more information about the desired PWM output? 

    I am going on the assumption that the desired configuration is where EPWM0B is a complementary output of EPWM0A.  Based on that assumption, there are multiple ways to generate a complementary output in up-down mode without using CMPB. 

    1. Using CMPA
      - Whenever a CAU occurs, force EPWM0A to output high, and force EPWM0B to output low
      - Whenever a CAD occurs, force EPWM0A to output low, and force EPWM0B to output high
    2. Using CMPA and the Dead-band submodule
      - Generate EPWM0A as your desired PWM output
      - Use Dead-band submodule to force EPWM0B to be an active-high complementary or active-low complementary of EPWM0A with zero rising or falling edge delay
      - For more information on the dead-band submodule, see section 2.6 in the SPRUFL3B user guide
      - Also, section 3.8 is a good reference section about deadband

    - Christina

  • TI__Expert 4745 points

    Foir a use case scenario to capture  ADC measurements using an external ADC what is the best approach to perform a double update rate synch pulse.

    The coherence of the 2 synch signals needs to be independent of software.  What is the typical approach to double update rate?

    >> Question: How do we do double updates in this scheme where the SyncOut pulse is only generated on the valleys or when counter reaches ZERO? Do we >> have to set a GPIO from ePWM_INT event and use external glue logic to OR this signal with SyncOut pulse? Assuming SyncOut pulse is set when counter

    >> reaches ZERO.
    >> Answer: TBCTL[SWFSYNC] is the only signal internally ORed with the syncout pulse.  

  • in reply to DaveB123
    TI__Expert 8785 points

    Dave,

    Can you elaborate more about the double update rate sync pulse?  For example, what is the desired PWM output?  Is there a requirement on when the sync pulse needs to occur?  How does the external ADC interact with the PWM output? 

    - Christina