MCASP2 master clock

Hi Mike,

Have you checked the TI81xx clock framework?

processors.wiki.ti.com/.../TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

Regards,
Pavel

Hi Pavel,

I did see it but was a bit confused. I see that in uboot macsp2 clock is set and also in linux-kernel as well.
In my case:
AUXCLK(OSC1) ---> CLKOUT0----> Codec chip (AUD_CLKIN0)-----------> mcasp2

any pointer on this (I have seen that my codec is generating required clock) but how do I tell prcm audio clock to select it ?

Thanks And Regards,
--Mike

Hi Pavel,

I need something like in the link e2e.ti.com/.../816917
with just a difference that MCASP2 clock source is AUD_CLKIN0 which is generated by the codec.

Thanks And Regards,
--Mike

Hi Pavel,

I have selected the pinmux to select AUD_CLKIN0 pin.

I am not sure about these two statements in u-boot:

__raw_writel(0x2, CM_AUDIOCLK_MCASP2_CLKSEL);
while (__raw_readl(CM_AUDIOCLK_MCASP2_CLKSEL) != 0x2);

And also in linux side what settings need to be done ?

Thanks And Regards,
--Mike

Mike,

mike A said:

I did see it but was a bit confused. I see that in uboot macsp2 clock is set and also in linux-kernel as well.
In my case:
AUXCLK(OSC1) ---> CLKOUT0----> Codec chip (AUD_CLKIN0)-----------> mcasp2

Note that McASP numbering starts from 0 in datasheet/TRM:

McASP2 base address is 0x4680_0000 (data port) and 0x4805_0000 (config port).

While in Linux kernel, the mcasp clocks starts from 1:

McASP2 module clocks are mcasp3_ick, mcasp3_fck (aux_clk) and mcasp3_ahx_ck (ahclkx)

AUD_CLKIN0 is xref0_ck.

For selecting AUD_CLKIN0 for input on McASP2 ahclkx (Transmit High-Frequency master Clock) pin:

McASP_AHCLK_CLKSRC[18:16] McASP2_AHCLKX_SOURCE = 0x0 = 000 : Source is AUD_CLKIN0 - Select the source clock of the MCASP2 AH clock transmit

So, do you need to provide AUD_CLKIN0/xref0_ck to the McASP2 ahclkx (mcasp3_ahx_ck) input?

See also the below e2e thread, which discuss AUD_CLKIN2/xref2_ck:

Regards,
Pavel

Hi Pavel,

On the evm the src is aud_clkin0 itself (i did a devmem), & my custom board its the same. How much clock frequency is needed for mcasp2 to driver ?

Thanks And Regards,
--Mike

Mike,

mike A said:

How much clock frequency is needed for mcasp2 to driver ?

I am not sure I understand your last question. Regarding clock frequency values, refer to the DM814x datasheet.

Regards,
Pavel

Hi Pavel,

I want to set my codec as master and mcasp2 as slave,
I have set following davicni-evm.c
#define AUDIO_FORMAT (SND_SOC_DAIFMT_I2S | \
SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF)

does this set mcasp2 as slave ?

Thanks And Regards,
--Mike

Hi Pavel,

Do I need to change the static u8 ti8148_iis_serializer_direction[] to work it in i2s mode ?

Thanks And Regards,
--Mike

Mike,

mike A said:

I want to set my codec as master and mcasp2 as slave,

The TI81xx audio ALSA driver sets audio codec (AIC3x) as master and McASP2 as slave by default:

McASP is configured as slave and AIC31 Codec is configured as master.

By default, codec is configured in master mode and McASP is used as slave.

McASP2 on the TI81xx EVMs operates in a slave mode (codec driving the bit clock and the frame sync)

Regards,
Pavel

Mike,

mike A said:

Do I need to change the static u8 ti8148_iis_serializer_direction[] to work it in i2s mode ?

See the below e2e thread:

Regards,
Pavel

Hi Pavel,

Looking at the post I am bit confused, there is a file davinci-i2s.c because of which I felt I2S format was supported, Is it really supported ?
BTW I am using the exsdk release but it says I2S is supported.

Thanks And Regards,
--Mike