We are currently using PCIe link between TMS320C6655 and Spartan 6 FPGA. We get past detect state and go into link training but basically we cannot get past link training. The Spartan 6 only supports 1 PCIe1.0 lane so the max link speed is going to be 2.5Gb/s even though the DSP supports PCIe2.0 and up to 2 lanes. We have been able to do some preliminary eye diagram analysis of DSP TX diff pair to FPGA and FPGA TX diff pair to DSP. The DSP TX diff pair to FPGA eye diagram is partially closed and the suspected problem whereas the FPGA TX diff pair to DSP look pretty good and appears to be within compliance. We have looked over DSP and FPGA device configuration and not found anything which has improved eye between DSP and FPGA. We have also looked at the common 100MHz clock we are supplying to both FPGA nd DSP and clocks look to meet PCIe1.0 jitter requirement. FYI...We currently have the Spartan 6 EVM and the TMS320C6657 EVM connected via a daughter card we previously developed for proof of concept and PCIe link is working okay in that application. We are open to suggestions to resolving this problem and currently working to get PCIe IBIS-AMI model to do some board level simulations.
James
