SN75DP130SSRGZR Application guide control register level

Jimi Huang

I met the ti (SN75DP130SSRGZR Datasheet & Application ) adjustment program can not modify the maximum word setting to BIOS firmware is write to, if there is a suggestion TI specification scratchpad support HBR2 firmware file to me

Jitter HBR2 5.4Gb/s Eye diagram mask error over DP1.2 spec

11Lane 2 - HBR2CPAT Eye Diagram Test (TP3_EQ)72.000-715E+01 %-500 m <= VALUE <= 500 m

Thank you5483.DP_port_CN6.rar

over 10 years ago

0 Peter Chen(ICP_FAE) over 10 years ago

TI__Intellectual 2480 points

The DP HBR was failing at lane 2 only and the problem is that its jitter is worse than other DP Lanes. The layout is critical especially in DP5.4Gbps application.

Besides, the layout modify in Lane2. You can follow the table 8 of datasheet (address 09/0Ah) for LANE2's EQ gain fine tuning.

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SN75DP130SSRGZR Application guide control register level