Please help my C6455 customer with the following questions about MDIO operation:
We are currently integrating a new Marvell PHY chip with the C6455 DSP and had some questions regarding the MDIO interface capabilities of the C6455.
The PHY we are integrating supports a paging system in the MDIO registers. The page is changed by modifying the value of register 22. Once the page has been modified, reads or writes to any other register will now access a different set of registers than the default range. It seems that this conflicts with the link status polling capability of the MDIO controller on the C6455. For example if we initiate a page change using the “USERACCESS0” register, we would need to guarantee that we can restore the page back to the default before the MDIO statemachine attempts to update the LINK status register by accessing the PHY STATUS register using MDIO.
Also, The PHY we are integrating with the C6455 supports an MDIO clock rate up to 12MHz. According to the C6455 documenation(section 7.14.4.1), the maximum supported frequency of the MDIO clock is 2.5MHz. Could you please confirm that we cannot run the MDIO clock on the C6455 faster than 2.5MHz even if the PHY supports an MDIO clock of 12MHz?
Is there a way we can temporarily disable the MDIO state machine from attempting to send any MDIO requests to the PHY until the software has restored the page on the PHY chip to the default page using the “USERACCESS0” register?
