DRA7xx_EVM DCAN

Ganesh Tenka

In DRA7xx_EVM i am accessing CAN , i was able to open a socket ,send the data using the socket and also able to read the data with another socket and also verified receiving data with masking and all in loopback mode.. But I am not getting the data on hardware pins to communicate with real device outside ..

In dtsi file,

dcan1: d_can@4AE3C000 {
            compatible = "bosch,d_can";
            ti,hwmods = "dcan1";
            clocks = <&dcan1_sys_clk_mux>;
            clock-names = "fck";
            reg = <0x4AE3C000 0x2000
                               0x4a002558 0x4>;
            flags = <0x5>;
            interrupts = <0 81 0x4>;
            status = "disabled";
        };
In dts file..

dcan1_default: dcan1_default_pins {
           pinctrl-single,pins = <
           0x3D0 0x40000 /* dcan1_tx */
                        0x3D4 0x60000 /* dcan1_rx */
               >;
       };

&dcan1 {
   pinctrl-names = "default";
   pinctrl-0 = <&dcan1_default>;
   status = "okay";
};

We shorted the resistor R611 at CAN_RX pin also..I have modified for CAN in dtsi as well as dts file....Am i wrong some where??

Regards,

Ganesh

over 10 years ago

0 Boyko Kazakov over 10 years ago

TI__Genius 10965 points

Hi Ganesh,
Did you check here how the nodes are added in the GLSDK?
permalink.gmane.org/.../119858

0 Ganesh Tenka over 10 years ago in reply to Boyko Kazakov

Expert 1770 points

Yeah I have added these two lines also..
d_can0 = &dcan1;
d_can1 = &dcan2;

0 Yanko Todorov-XID over 10 years ago

TI__Mastermind 29520 points

Hello Ganesh,

I checked on my DRA7xx_EVM the state of DCAN1 pads.
CTRL_CORE_PAD_DCAN1_TX[3:0] DCAN1_TX_MUXMODE
root@dra7xx-evm:~# omapconf read 0x4A0037D0
0000000F

CTRL_CORE_PAD_DCAN1_RX[3:0] DCAN1_RX_MUXMODE
root@dra7xx-evm:~# omapconf read 0x4A0037D4
000E000F

0xF default value in these bit-fields defines that the pad is Driver off. It corresponds to dcan1_pins_sleep in dra7-evm.dts
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
0x3d0 (MUX_MODE15) /* dcan1_tx.off */
0x418 (MUX_MODE15) /* wakeup0.off */

You must set DCAN1 pads in dcan1_pins_default:
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */

Please use following steps for enable DCAN:
root@dra7xx-evm:~# ip link set can0 type can bitrate 500000 loopback on
root@dra7xx-evm:~# ifconfig can0 up
[ 723.023787] c_can_platform 4ae3c000.can can0: setting BTR=0504 BRPE=0000

root@dra7xx-evm:~# omapconf read 0x4A0037D0
00010000

Now DCAN1 pads are in default state and they are connected to DCAN module.

Best regards,
Yanko

0 Ganesh Tenka over 10 years ago in reply to Yanko Todorov-XID

Expert 1770 points

cpu_is_omap(): CONFIG_SOC_BUS not enabled in kernel!
Hello Yanko,

1. I am configuring 0x4A0037D4 as RX pin instead of 0x4A003818 for CAN, it should also work no?
2.When i executed this command i am getting,
root@dra7xx-evm:~# omapconf read 0x4A0037D0
Assuming cpu is OMAP(legacy kernel): CONFIG_SOC_BUS not enabled in kernel!
00040000
omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!! why?

Regards,
Ganesh

0 Yanko Todorov-XID over 10 years ago in reply to Ganesh Tenka

TI__Mastermind 29520 points

Ganesh,

I recommend you to apply following configurations in pad registers:

Enable DCAN1_RX_INPUTENABLE as set CTRL_CORE_PAD_DCAN1_RX[18] DCAN1_RX_INPUTENABLE - 0x1: Receive mode is enabled
Disable Pull up/down as set CTRL_CORE_PAD_DCAN1_RX[16] DCAN1_RX_PULLUDENABLE - 0x1: Disables weak Pull Up/Down

Disable DCAN1_TX_INPUTENABLE for TX pad by the register CTRL_CORE_PAD_DCAN1_TX[18] DCAN1_TX_INPUTENABLE

For correct DCAN pad configuration you must use registers:

CTRL_CORE_PAD_DCAN1_TX - 0x4A00 37D0
CTRL_CORE_PAD_DCAN1_RX - 0x4A00 37D4

Best regards,

Yanko

0 Ganesh Tenka over 10 years ago in reply to Yanko Todorov-XID

Expert 1770 points

Ok Thank You Yanko.. I am getting data on the bus with this pin configuration,
0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */..

0 Ganesh Tenka over 10 years ago in reply to Ganesh Tenka

Expert 1770 points

Hello Yanko,

Actually when i am trying to write continuously on the bus with no other device connected to the bus(or no device receiving )... I am getting "no buffer space available" error after 26 times.. i.e., all the tx msg objects allocated for CAN are filled, correct? But in the driver if you see c_can.c,

#define C_CAN_NO_OF_OBJECTS 32
#define C_CAN_MSG_OBJ_RX_NUM 16
#define C_CAN_MSG_OBJ_TX_NUM 16

No of msg objects for C_CAN_TX and C_CAN_RX are 16 na?..So I should get error after 16 times na?
Also i think for CAN total 64 msg objects available then why in macro fixed to 32 ?

Thanks & Regards,
Ganesh.

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DRA7xx_EVM DCAN