Hi,
I have a question about AM335x DDR register configuration.
In TRM(spruh73l) page.1460, there are ddr_cmd0_ioctrl register.
The question is about bit[9:8](io_config_sr_clk) of this register. It seems that this bit is Read-only.
How to configure Slew Rate? I guess it's typo and Read/Write is correct.
Is my guess right?
Because other ddr_cmdn_ioctrol bit[9:8] is R/W and it's description is written as follow:
///////////////////////////////////////////////////////////////
Only ddr_cmd0_ioctrl[9:8] are used to control io_config_sr_clk.
///////////////////////////////////////////////////////////////
best regards,
g.f.
