TCI6486 EMAC FATAL Error Ownership bit not set in SOP buffer

Aswathy A

Hi,

We are having a custom board of TCI6486 DSP. The EMAC1 interface is used for Ethernet with RGMII PHY. It is working at 1Gbps speed.

We have developed a code for supporting 1024 channel processing at a time. It include ethernet packet receive & some transmit in core0.
Major emac transmit and Tsip processing is divided among 4 other cores (1,2,3,4).

DDR2 memory in cacheable configuration is used for ethernet packet buffers. EMAC BD's are in L2.
L1P, L1D cache is enabled in all cores.
We are handling EMAC interrupts using csl library provided by TI.
EW_INTCTL register is cleared for the specific interrupt while inside the ISR.

SL2 and DDR memory cache coherence issue is taken care inside the code using cachewb and cacheinv wherever required.

The issue is on a very huge load on all channels, FATAL error is occurring after some hours or may be overnight.
All the time the error is Ownership bit not set in SOP buffer for Transmit channel 0. Tx channel 0 is used by core0.
Fatal error is not occurring in other cores.

Can any help be given for the issue.?

over 10 years ago

0 Raja over 10 years ago

TI__Guru* 81335 points

We are working with team to answer this post. Thank you for your patience.

0 Javier Malave-Bonet over 10 years ago

TI__Expert 5805 points

Hi Aswathy,

I have notified someone who has worked previously with TCI6486 EMAC to take a look at this item. We will be working on it together. We will get back to you as soon as possible.

Regards,
Javier

0 Aswathy A over 10 years ago in reply to Javier Malave-Bonet

Prodigy 140 points

For clarity, i am not using mcsdk. We have developed the code from csl libraries provided by TI.
The csl version is very old. the version number is 03_00_03_00. We are trying to develop with latest csl. But that will take some time. So if you could provide some solution for my problem, it would be helpful.

The dsp chipset used in TMS3TCI6486CCTZ625. silicon revision 0x00120091 device id 0x1009102f.

The code is developed in ccs5.3.

0 Aswathy A over 10 years ago in reply to Aswathy A

Prodigy 140 points

The problem is solved.

The value put in TPCFG register for channel 0 of EMIC was not sufficient. When we increased the value, the fatal error is not occurring.

Thanks for your support.

0 Raja over 10 years ago in reply to Aswathy A

TI__Guru* 81335 points

Hi Aswathy,
Thank you for the update.

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TCI6486 EMAC FATAL Error Ownership bit not set in SOP buffer