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DRA320DM8148 MMC Interface RESETDONE

Martin Ko
Prodigy 120 points

Hello,


i want to access the MMC/SD_1 Interface of the DRA320DM8148. I have done the following prerequisites:

- Pinmux for MMC1

REG(PINCNTL8)  |= MUXMODE_SD0_CLK;
REG(PINCNTL9)  |= MUXMODE_SD0_CMD;
REG(PINCNTL10) |= MUXMODE_SD0_DAT0;
REG(PINCNTL11) |= MUXMODE_SD0_DAT1;
REG(PINCNTL12) |= MUXMODE_SD0_DAT2;
REG(PINCNTL13) |= MUXMODE_SD0_DAT3;	
REG(PINCNTL35) |= MUXMODE_SD0_DAT4;
REG(PINCNTL36) |= MUXMODE_SD0_DAT5;
REG(PINCNTL41) |= MUXMODE_SD0_DAT6;
REG(PINCNTL42) |= MUXMODE_SD0_DAT7;
REG(PINCNTL72) |= MUXMODE_SD0_SDCD;

- Enable clocks

	tms320dm8148_clock_enable(CM_ALWON_L4LS_CLKCTRL);	//L4LS
	tms320dm8148_clock_enable(CM_ALWON_CONTROL_CLKCTRL);

	
 //these functions write 0x2 to the apropriate clk-register
	REG(PRCM_REGS_BASIS + CM_ALWON + 0x000) = 2;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x004) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x008) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x00c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x010) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x014) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x018) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x01c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x020) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x024) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x028) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x02c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x030) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x140) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x144) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x148) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x14c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x150) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x154) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x158) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x15c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x160) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x164) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x168) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x16c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x170) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x174) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x178) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x180) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x184) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x188) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x18c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x190) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x194) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x198) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x19c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1a8) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1b4) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1b8) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1c4) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1d0) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1d4) ;
 	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1dc) ;
// :O 	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1e0) ;
 	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1e4) ;
 	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1e8) ;
 	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1ec) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1f0) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1f4) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1f8) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x1fc) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x200) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x204) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x218) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x21c) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x220) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x224) ;
	tms320dm8148_clock_enable(PRCM_REGS_BASIS + CM_ALWON + 0x228) ;

	REG(CM_ALWON_MMCHS_0_CLKCTRL) =  MODULEMODE_ENABLE; // reset value 0x30000
	// wait for ready set
	while((REG(CM_ALWON_MMCHS_0_CLKCTRL) &  MODULEMODE_IDLEST));


After that I do a reset of the MMC1 Interface. Here is the code
So write SOFTRESET to MMC1_SYSCONFIG  and the poll for RESETDONE in SYSSTATUS.
But RESETDONE never goes ready (to 1).

The question is why MMC1-Interface never gets ready. Is there any prerequiste thats not fullfilled?

Is there any StartKit-like software for the TMS329DM8148.



BR Martin

  • 0
    Prodigy 120 points

    Sorry for the formating issue.


    Here is the last part of the post:

     I have used my working code from the AM335x. The part that fails is the SOFTRESET. After doing this the init function polls for RESETDONE. But this bit never goes hight. So my question is, is there any other prerequisites. What I have confugred so far is:

    • Pinmuxing of MMC1
    • Enable all Clocks in CM_AWLON

    Is there any StartKit-like software for the TMS329DM8148.