Does each parameter of NO.1 to NO.12 in Table 7-66 on the datasheet indicate the real trace (the etch) length, not horizontal or vertical length?
Best regards,
Daisuke
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Does each parameter of NO.1 to NO.12 in Table 7-66 on the datasheet indicate the real trace (the etch) length, not horizontal or vertical length?
Best regards,
Daisuke
Yes, these are real trace lengths.
Hi Biser,
Thank you for your reply.
I have an additional question.
What is "AS"? Does this indicate the length to route down lower than each DDR3 memory?
For the longest CK and ADDR_CTRL Manhattan distance: "Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils. The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8."
If non-A8 is the longest, is the extra 300 mils available?
Best regards,
Daisuke
AS makes sense if you have more than one memory chip and Vtt termination resistors. This is the stub length from the address/control trace to the memory pin. If you use a single memory without Vtt termination you can disregard it.
The extra 300mil are added to the longest manhattan length, no matter which address/control line it is. This 300mil accounts for the PCB thickness when routing the traces on more than one layer.
Hi Biser,
Thank you for your reply.
Are NO.6 (AS length) and NO.7 (AS skew) applied to ADDR_CTRL net class only? Are NO.8 (AS+ and AS- length) and NO.9 (AS+ and AS- skew) applied to CK net class only?
If routing the traces only on one layer, should the extra 300mil not be added?
Best regards,
Daisuke
Daisuke Maeda said:Are NO.6 (AS length) and NO.7 (AS skew) applied to ADDR_CTRL net class only? Are NO.8 (AS+ and AS- length) and NO.9 (AS+ and AS- skew) applied to CK net class only?
Yes, your understanding is correct.
Daisuke Maeda said:If routing the traces only on one layer, should the extra 300mil not be added?
I don't see how you can route all address/control signals on a single layer. The formula is valid for all cases.