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DM8148 McASP

Madhura Shetty
Intellectual 810 points

Hi,

We are using 2 McASP interfaces between FPGA and DM8148 processor. I would need ACLKX, AFSX, AXR(bit clk, word clk, data) for transmission and ACLKR, AFSR,AXR, AHCLKR (bit clk, word clk, data and master clk) for reception. But in DM8148  device AHCLKR pins are not provided in any of McASP terminals. But in timing requirements of McASP (Table 8-78) this signal is mentioned. 

Regards

Madhura

  • 0
    TI__Guru**** 170625 points
    Hi Madhura,

    You can use McASP0/1 AHCLKR ports as input only and provide one of the below set of signals: aud_clkin0/1/2, auxosc_xi, atclk0/1/2/3.

    See DM814x TRM, Figure 2-12. Audio Clock Structure and Figure 2-168. McASP_AHCLK_CLKSRC Register
    [11:9] McASP1_AHCLKR_SOURCE - Select the source clock of the MCASP1 AH clock receive
    [5:3] McASP0_AHCLKR_SOURCE - Select the source clock of the MCASP0 AH clock receive

    BR
    Pavel