Bits set in EDMA3 Event Register for global region after cold boot

Hi Raja,

Thanks for the warm welcome.

Some further research revealed that I had apparently misunderstood how the Event Enable Register is to be used. I had assumed from reading the EDMA3 documentation that enabling events for a given channel was necessary in order to manually start a transfer by writing to the Event Set Register. It appears, however, that this is not the case, and writing to ESR will start a transfer on the corresponding channel even if the channel's EER is not set. This seems to be the mechanism by which the CSL is able to execute transfers correctly.

Unfortunately, this still leaves the initial value of the Event Register unexplained. It no longer appears to be a pressing matter, but a clarification as to what is causing that phenomenon would still be greatly appreciated.

Again, thank you for your time,
Lukas

Lukas,

The cold-reset initial state of the ER registers will be all 0's. But a lot of code can run between when you apply power or cold reset until the time you look at these register bits.

You can determine from the C6678 data manual which peripheral events these bits are tied to, and that may give you a hint as to why they were enabled. No code would set the ER bits unless it was making use of those peripheral events. This may help lead you to recognizing some difference between your two boards and how they are used in your current configurations.

A good point that this brings up is that you will want to make sure all bits like these are in a known and controlled state when you start your application running. The EDMA3 driver code does not (in my experience, with older code) attempt a thorough job of returning all bits to their reset states. This is probably good, to avoid destroying some configuration that was done previously that should not be temporarily disabled by clearing bits.

For your application, you may want to clear all the ER bits as part of the EDMA3 initialization process. Here is some code I have used based on register-level CSL, so the struct pointer and other things may need to be changed for your case:

/* DMA Channel initialization */
EDMA3_CC_Regs->QUEPRI = 0x00000000; // max priority for all TCs
EDMA3_CC_Regs->EECR = 0xFFFFFFFF; // clear event enables
EDMA3_CC_Regs->EECRH= 0xFFFFFFFF; // clear event enables
EDMA3_CC_Regs->ECR = 0xFFFFFFFF; // clear any pending event bits
EDMA3_CC_Regs->ECRH = 0xFFFFFFFF; // clear any pending event bits
EDMA3_CC_Regs->SECR = 0xFFFFFFFF; // make sure all possible
EDMA3_CC_Regs->SECR = 0xFFFFFFFF; // excess events are removed
EDMA3_CC_Regs->SECR = 0xFFFFFFFF; // from trigger registers
EDMA3_CC_Regs->EMCR = 0xFFFFFFFF; // and then clear EMR
EDMA3_CC_Regs->IECR = 0xFFFFFFFF; // clear interrupt enables
EDMA3_CC_Regs->IECRH= 0xFFFFFFFF; // clear interrupt enables
EDMA3_CC_Regs->ICR = 0xFFFFFFFF; // clear any pending IPR bits
EDMA3_CC_Regs->ICRH = 0xFFFFFFFF; // clear any pending IPR bits
EDMA3_CC_Regs->CCERRCLR = 0xFFFFFFFF;

Regards,
RandyP