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A question about using C5509A's McBSP as SPI Slave

Oliver Chen
Intellectual 725 points
Other Parts Discussed in Thread: TMS320VC5501

Dear All,

I've a question about using C5509A's McBSP as SPI Slave. The desired SPI protocol is similar to the one used in ordinary SPI Flash. In such protocol the SPI /CS signal remain asserted (Lo) during the command, address, write/read data phases. As an example, you can check the timing diagram in P. 25 Figure 7 of the following datasheet of some SPI Flash:

www.winbond.com/.../w25q64cv_revh_052214[2].pdf

However, according to the following paragraph in P. 6-15 of SPRU592E (TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide), it seems that such SPI-Flash-like protocol is not possible for the SPI Slave using McBSP because /CS must be de-asserted:

The McBSP requires an active edge of the slave-enable signal on the FSX
input for each transfer. This means that the master device must assert the
slave-enable signal at the beginning of each transfer, and deassert the signal
after the completion of each packet transfer; the slave-enable signal cannot
remain active between transfers.

I'm wondering whether it is possible to use McBSP to implement an SPI Slave supporting SPI-Flash-like protocol?

Regards,

Oliver

  • 0
    TI__Genius 12575 points

    Hi Oliver, 

    As mentioned in C5509A  MCBSP user guide while operating as SPI,  requires slave enable signal on FSX to be asserted at the beginning of each transfer and de-assert at the completion of the transfer and cannot remain active in between the transfers. 

    If you are looking for SS signal to be active between the transfers then this is not supported in C5509A device.

    Hope this clarifies. 

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Intellectual 725 points
    Dear Vasanth,
    OK, I understand.
    Anyway, thanks for your prompt reply and information!

    Regards,

    Oliver