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Timer output pin TOUT0 on C5517?

Olaf Albert
Intellectual 320 points

We are migrating from 'C5509 to 'C5517. The former one has a TOUT0 output pin for a timer. The new one does not. We use it to start a ADC conversion with a large variety of sample rates (500 ksps ... 500 sps).

Is there any chance to get a divided sysclk onto a pin with low jitter?


Thank you for the answer!

  • 0
    TI__Genius 12575 points

    Hi,

    Yes C5517 doesn’t have the option of TOUT like in the case of C5509 device.

    With respect to your question on getting a divided sysclk onto a pin. There exists a CLKOUT pin for debug purpose only, the DSP includes a CLKOUT pin which can be used to tap different clocks within the clock generator. The SRC bits of the CLKOUT configuration register (CLKOUTCR) can be used to specify the source for the CLKOUT pin. The CLKOUT_DIV bits provide the various options to divide down the system clock to be used on the CLKOUT pin. The CLKOUT_GZ bit can be used to enable and disable the CLKOUT pin's output buffer.

    Hope the above information helps.

    Regards

    Vasanth

  • 0 in reply to Vasantha K
    Intellectual 320 points

    Hi,

    Thank you for the fast response!

    The information you gave I already read in the data sheet SPRS727C and technical reference document SPRUH16. The pitty is that the register CLKOUT_SRC[3:0] allows me to select eight times the system PLL clock but never a timer output. The only other relatively free programmable divider would be the SAR clock (the ADC) but the ADC I would like to use for other purposes than just clock generation - 'of course' with an other clock frequency.

    Here are my further questions:

    1. Is there no other pin I can use to output the divided system clock (500 Hz ... 500 kHz from 200 MHz source clock) with low jitter?

    2. What means 'only for debugging purposes' for the CLKOUT pin? Is it just another type of output stage that has different current /slew rate limits? Or is its signal quality somehow limited (see the unanswered C5517 CLKOUT jitter problem topic in the forum)?

    Thank you for your answer!


    Regards,

    Olaf

  • 0 in reply to Olaf Albert
    TI__Genius 12575 points

    Hi,

    Below are my response for your Questions.

    A1. Yes I believe there is no dedicated pin which accomodates your requirements.

    A2. The clock pin has not been characterized as a clock source like rise/fall time, duty cycle etc. Thats the reason this pin is not recommended to be used as the clock source pin.

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Intellectual 320 points
    Hi,

    Here are my remarks to your answers.

    1. So the only solution is chosing an other DSP?! (In your email was wirtten something about GPIO but I guess this would not be without jitter in the size of several sysclk cycles...)
    2. OK. This would not be a problem to me as long as I can connect an CMOS input to it. Since I have no appropriate internal source it does not matter anymore.

    I have to confess that I am disappointed.

    Regards,

    Olaf