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How to reset TPS65217C PMIC with AM335x .



Hello Biser,
Now we could able to generate a 10.625uS pulse width on nRESETIN_OUT signal by programming PRM_RSTTIME Register with max count of 255. In line with this query we have another problem on the board.
We are powering  PGOOD signal of PMIC is connect to PWRONRST on of the processor. Our requirement is upon every Watchdog Timer Reset/ SW Warm Reset we want to power cycle the board. When I connect nRESETIN_OUT signal of the processor with nRESET pin of the PMIC I don’t see any RESET action with PMIC. I am not able to find the RESET timing requirements in the TPS65217C PMIC datasheet. How to address this issue?

But when I press S9 (Refer attached schematics)reset switch of the processor or S11 (Refer attached schematics)switch of PMIC (for more than 8 sec) with nRESETIN_OUT signal connected to PMIC nRESET input pin PMIC is turning off and nRESETIN_OUT signal held low (Looks like a deadlock situation) until I disconnect the Processor nRESETIN_OUT signal from PMIC nRESET input pin. Is it not recommended to connect nRESETIN_OUT signal of processor to PMIC nRESET input pin?

  • Some test is deleted unfortunately in previous post. Refer the below one if you confuse with first post.
    Hello Biser,
    Now we could able to generate a 10.625uS pulse width on nRESETIN_OUT signal by programming PRM_RSTTIME Register with max count of 255. In line with this query we have another problem on the board.
    We are powering AM335x with TPS65217C PMIC. PGOOD signal of PMIC is connect to PWRONRST on of the processor. Our requirement is upon every Watchdog Timer Reset/ SW Warm Reset we want to power cycle the board. When I connect nRESETIN_OUT signal of the processor with nRESET pin of the PMIC I don’t see any RESET action with PMIC. I am not able to find the RESET timing requirements in the TPS65217C PMIC datasheet. How to address this issue?

    But when I press S9 (Refer attached schematics)reset switch of the processor or S11 (Refer attached schematics)switch of PMIC (for more than 8 sec) with nRESETIN_OUT signal connected to PMIC nRESET input pin PMIC is turning off and nRESETIN_OUT signal held low (Looks like a deadlock situation) until I disconnect the Processor nRESETIN_OUT signal from PMIC nRESET input pin. Is it not recommended to connect nRESETIN_OUT signal of processor to PMIC nRESET input pin?

    Thanks & Regards,
    Praveen Kajjam.
  • I think you have created a dead loop here. Once nRESETIN_OUT goes low it resets the PMIC, placing it into OFF state and all power supplies are switched off. To start the PMIC from this state the PMIC nRESET pin must go high. I think you will need some external circuitry, supplied from an "always on" power rail and driven from the nRESETIN_OUT processor signal to generate a low pulse on the  PMIC nRESET pin.

  • Hello Biser,

    Thanks for your quick reply. Do you suggest any recommended circuit for above solution?
    I am not able to find any reset timing requirements for nRESET pin of TPS65217C PMIC in datasheet. Do you have any additional info regarding this? I only see one spec "nRESET pin deglitch time = 30mS". What does this indicate?

    Thanks & Regards.
    Praveen Kajjam.
  • Praveen Kajjam said:
    Thanks for your quick reply. Do you suggest any recommended circuit for above solution?

    No, there are no reference designs for such a use case. I suggest you try some sort of one-shot circuit for this.

    Praveen Kajjam said:
    I am not able to find any reset timing requirements for nRESET pin of TPS65217C PMIC in datasheet. Do you have any additional info regarding this?

    Check the RESET PIN (nRESET) section in the TPS65217C datasheet.

    Praveen Kajjam said:
    I only see one spec "nRESET pin deglitch time = 30mS". What does this indicate?

    This is the debounce time of the input, meaning that a pulse shorter than 30ms will be rejected on this input.

  • Hello Biser,
    In RESET PIN (nRESET) setion it state that"The device will remain powered down as long as the nRESET pin is held low but
    for a minimum of 1 second." But what is the minimum low pulse width required on nRESET pin to trigger a Reset action through nRESET pin?

    Can i understand from the nRESET pin deglitch specification that, i need a pulse width of more than 30mS to assert Reset action thought nRESET pin?

    Thanks & Regards,
    Praveen Kajjam
  • Hello Biser,
    I got some insight into this solution now but I still have some concern related to dead loop scenario. TRM says nRESETIN_OUT is an open drain output and requires external pull up. Also the nRESET pin of PMIC has internal 100K pull-up terminated to a always on supply (Not sure which voltage it is). When nRESETIN_OUT drives nRESET pin low PMIC output regulators are turned off and processors will lose its power. In that case processor should de-assert the nRESET and it should go to logic high through the internal pull-up. Why it is not happening?

    Thanks & Regards,
    Praveen Kajjam.
  • Have you checked this signal with a scope to see what's happening?

  • Hello Biser,
    It is captured as always low with the scope until i disconnect nRESETIN_OUT from nRESET pin of PMIC. After disconnecting it will start standard cold boot process and operates in normal condition.

    Thanks & Regards,
    Praveen Kajjam.
  • The signal gets grounded through the external 10kOhm pullup to VDDSHV6, which has probably saved your processor nRESETIN_OUT pin, as I suspect that the PMIC internal pullup is to a higher voltage, probably PMIC input voltage.