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TI 66AK2E02 Interface for 8bit Digital Data IN, OUT.

Magesh Subramani
Prodigy 110 points

Hi Ti Support Team,

We are building new board and we had chosen TI 66AK2E02 device (1 ARM + 1 DSP core)  as MAC processor. The requirement for MAC processor is 1 ARM + 1 DSP or ARM and running at 1GHz. But it seems above mentioned TI processor doesn't support parallel digital data IN (8bits) and our requirement is to send two sets of synchronous 8bit parallel data from Y, Z chipset to MAC, as well to get controlled (read_n, refer note) 8 bit parallel data output from MAC to X chip. Here I have attached our interface requirement.  The X,Y and Z chips doesn't support SPI interface. Please suggest us methods to interface with about TI processor. If you think some other TI processor with different digital IN interfaces (Mac BSP) would help, then requesting you to share the information.  Thanks.

/ Magesh S

  • 0
    TI__Mastermind 43660 points

    Hello Magesh,

    Does X, Y, Z devices have only parallel interface ?

    The 66AK2E02 device has EMIF16 only and it may not suitable for your requirement. Only the C665x Keystone devices have two channels of McBSP, but there is no ARM core on these devices.

    I would suggest you to prefer serial interfaces for X, Y and Z devices.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 110 points
    Thanks Senthil. We are looking for 1 ARM + 1 DSP or 2 instance of ARM core, hence C665x is not a right choice.

    Yes. The X,Y and Z device doesn't support serial and provides either 8 bit digital IN or OUT.

    We had option of converting EMIF interface to 8 bit Digital IN (asynchronous to synchronous) and it solves interfacing with X device. In 66AK2E02 device is it possible to configure two EDMA instance (or two DMA channel) with independent memories for write and read buffers and initiate time division multiplexed write and read on EMIF interface. If YES then we could explore further on this. Please let me know your comments.

    Best Regards,
    Magesh S
  • 0 in reply to Magesh Subramani
    TI__Expert 6815 points

    Hi Magesh,

    The EMIF is designed to operate with asynchronous memories/FPGA. It does not require external clocking to sync data like you have with X, Y and Z. If you haven't already, please take a look at the EMIF16 users guide to evaluate the requirements for your interface. I will be happy to address your concerns.

    Magesh Subramani said:
    We had option of converting EMIF interface to 8 bit Digital IN (asynchronous to synchronous)

    Could you clarify this statement?

    Assuming X, Y and Z are asynchronous interfaces:

    You could hook them up to three of the EMIF16 chip enables. Each chip enable has it own data space that can be accessed by EDMA masters. You bandwidth requirement of 48 * 3 = 144Mb/s can be handled by the EMIF (however turnaround time will negatively impact the bandwidth, see below).

    You can use one EDMA channel each for "read Y", "read Z" and "write X" and assign them all to a single EDMA transfer controller which can easily handle the bandwidth (details in EDMA3 users guide). Note that you will not be able to perform "concurrent" reads to Y and Z since they are on different chips selects and there exists a finite, but programmable turnaround time to switch between chip selects (turnaround defaults to 3 EMIF clock cycles). But if your objective is to perform read Y --> read Z --> write X as fast as possible, you can chain the 3 channels so that completion of "read Y" immediately triggers "read Z" which further triggers "write X". If you need to execute the transfers with a specified time period, you can configure the on-chip timers to periodically generate timer event interrupts to EDMA. So multiplexing can be achieved in various ways.The EDMA3 users guide has details on how to program the EDMA for chaining and event interrupts.