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Hyperlink hang on C6678

Hi Champs,

we have an occasional, random hang after Hyperlink initialization.

The procedure works in most cases but sometimes we see the nfempty1 bit in the Status Register set. This bit indicates that the Master Command FIFO is not empty. It seems we can not clear this bit in SW. The only way to recover from that seems to be a HW reset which of course is not desirable.

Question: How can we clear this bit in SW to be able to re-establish the link? Or is there any other workaround to re-establish the link?

Kind regards,

one and zero

  • Juergen,

    Is the issue re-producible in C6678 EVM with MCSDK example? If yes, please post the procedure to re-produce. Thank you.

     

  • Hi Raja,

    as stated this is a random issue so not easy to reproduce. This was observed on a customer board. Initialization is based of MCSDK.

    I'd like to get an answer to my question, which would allow to easily address this issue.

    Question: How can we clear this bit in SW to be able to re-establish the link? Or is there any other workaround to re-establish the link?

    Kind regards,
    one and zero
  • Hi,

    Without the hyperlink reset, Not able to clear nfempty1 bit in the Status Register. The reset bit must be toggled to recover from this error.

    Thanks,
  • Hi Ganapathi,

    I'm sorry, but I do not understand your answer. Which reset bit needs to be toggled?

    We tried Control Register reset bit but that had no effect.

    Kind regards,

    one and zero

  • Hi,

    I need an answer on this topic. Could somebody please confirm if resetting the nfempty1 bit in the Status Register is possible in SW.
    If yes please provide the instructions on how to do it.

    Thanks and regards,
    one and zero
  • Hi,

    I suggested Control Register reset bit for reset the hyperlink to clear the nfempty1 bit. This is the possible workaround for clearing the nfempty1 bit in software. if it is not working better to give hard reset to clear the status register bits.

    Thanks,
  • Hi,

    sorry your answer is not clarifying the issue. Is Control Register reset bit clearing the nfempty1 bit or not? Our observation is that it's not. Is this supposed to work? According to documentation I would say yes. From the Users Guide: "When this bit is set, all internal state machines are reset"
    Please confirm if the Control Register reset bit is actually clearing the nfempty1 bit.
    If not please document it accordingly.
    As of now the only way to clear it seems to be a HW reset.

    Kind regards,
    one and zero

  • one and zero,

    From my experience, when the Serdes Tx parameters configured are too bad, sometimes I will come into the above situation, e,g., Status register: 0x04402097 where nfempty1 bit is set.

    In the following steps I tried to recover this by doing Hyperlink reset via Control Register bit 0 from both-end. My observation is that this nfempty1 bit can't be cleared.

    I believe in document, reset to 0 means HW reset, not SW reset.

    Regards, Eric

  • Hi

    I provided some suggestions offline on possible PSC initiated localized reset for the module.

    We got additional clarity from the IP owner on the working of the software reset - which I am pasting here

    The reset bit is not intended to be a fix for link failures; it is intended to be used for changing modes. That is when entering loopback, the reset bit will inform the remote of a shutdown and properly bring down both ends of the link.

    The serial_stop bit is intended to stop local activity from being sent to the remote. It should be set prior to setting the reset or loopback bits to ensure local transactions have completed.

    The rpend bit indicate that there are transaction in flight, and when set bringing down the link or resetting the module this should be cleared, otherwise it will cause the internal system interconnect bus to never get the response. Remote Pending Request, indicates that a remote operation is currently pending or in flight. The user should monitor this bit after setting serial_stop and before changing iloop or reset register bits.

    The only state machines in Hyperlink are in the serial MAC and PCS layers. The reset only resets the serial logic. It does not flush outstanding transactions nor does it reset registers. The only way to reset the internal interconnect bus interface is to reset the module. But resetting the module will indeed flush any pending request, and cause the remote to see a link failure.

    Since the Hyperlink binds the busses in the two devices together, in the catastrophic case of a link failure both devices should be reset.

    The link failing is the root issue, diagnosing this and resolving it is key.

  • Some suggestions from the team on trying to root cause the stability/reliability/periodic failure issue

    What we have seen that causes most Hyperlink reliability issue is …
    1) Board layout, failure to maintain impedance. Impedance should be constant.
    2) Board layout, adding loops or wiggles to match length between lanes. This is not necessary as the Hyperlink can internally deal with over 13 inches of difference between the lanes. And since the distance spec is 7.8 inches max, adding wiggles only impacts return loss and impedance.
    3) Board layout, adding connectors, connectors affect return loss, impedance and max link speed.
    4) Board layout, poor clearance of differential signals to power planes or other noise sources.
    5) SW Pre and post cursor setting setup. The pre and post cursor settings (pre emphasize the line) and try to make up for some impedance issues. Ideally these can be determined via SLTK.

    Other things to check are…
    Disable dynamic power management, or at least set it to startup in the long mode. Some SERDES are not very good at recovering from lane enables and disables.