Platform edit RWIX

The link step does not fail but there are issues at runtime. I have working project which was tested a hundred times and when I try to move memory map description from .cmd file to platform by moving this

DDR3: o = 0x80000000 l = 0x80000000

to list in Edit Platform wizard, I have weird behaviour of program. Diff shows that memory maps are equal in both cases except that "I" attribute. I don't completely understand how this attribute can affect the runtime flow given that memory maps are equal.

Sam,
the only thing I can do is to make a post in the compiler forum on your behalf. But, can you also tell me which platform are you using for the working version of your app? There could be other differences between the platform in the working version of the app, and the new version with a platform created by the Wizard.
If you can also post the console output for both apps, that would help too.

For the working version I use ti.platforms.evm6678 and linker .cmd file.

I don't create new platform. I modify ti.platforms.evm6678 by creating a row for DDR3 as above and remove .cmd file. "I" attribute disappears from .map file and program ruins (with internal error of HeapMemMP module). I'll try to investigate at which point this happens.

Sam,
the response to my post on the compiler forum indicates that the attribute "I" should not have any effect at runtime. Only way that attribute would matter if you tried to allocate sections to memory objects with specific attributes, which most likely you are not doing.

Actually I don't know how current post get into TI-RTOS forum. I was sure that I posted to CCS forum.

So, I tried to isolate this problem by creating new project. But program executes in similar way with "I" attribute and without it. 

In my real world project issue persists however. I can not move memory definitions from .cmd to platform.

Here is more detailed description of what happens.

1. In .cmd file I have the following:

MEMORY {
//	L2SRAM:		Defined in platform
//	L1PSRAM:	Defined in platform
//	L1DSRAM:	Defined in platform

    SHRAM:           o = 0x0C000000 l = 0x00400000   /* 4MB Multicore shared Memory */

    CORE0_DDR3:      o = 0x80000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE0 */
    CORE1_DDR3:      o = 0x81000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE1 */
    CORE2_DDR3:      o = 0x82000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE2 */
    CORE3_DDR3:      o = 0x83000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE3 */
    CORE4_DDR3:      o = 0x84000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE4 */
    CORE5_DDR3:      o = 0x85000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE5 */
    CORE6_DDR3:      o = 0x86000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE6 */
    CORE7_DDR3:      o = 0x87000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE7 */
    DDR3:			 o = 0x88000000 l = 0x08000000   /* Shared DDR3 */
    DDR3_IPC:		 o = 0x90000000 l = 0x60000000   /* Shared DDR3 used by shared region */
    DDR3_HLNK:		 o = 0xF0000000 l = 0x10000000   /* 256MB hyperlink window in DDR3 */
}

In platform there are definitions for L1 L2 memories.

2. Project is built 8 times for every core and all the private data is put into COREX_DDR3

3. I have 1 initialized buffer of around 1 MB wide: 

#pragma DATA_SECTION (test_data, ".test_data");

static uint8_t test_data[] = { 0xBE, 0xBA, 0xAD, 0xAB, 0x00, 0x00, .... 1 MB }

which is located in DDR3 alone. The rest of "DDR3" region is empty.

Program.sectMap[".test_data"] = DDR3;

Nothing special.

4. So, memory map is following:

******************************************************************************
               TMS320C6x Linker Unix v8.0.1                    
******************************************************************************
>> Linked Wed Mar 25 13:51:03 2015

OUTPUT FILE NAME:   <very_good_project.out>
ENTRY POINT SYMBOL: "_c_int00"  address: 0087e800


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  L2SRAM                00800000   00080000  0007e4ee  00001b12  RW X
  L1PSRAM               00e00000   00008000  00000000  00008000  RW X
  L1DSRAM               00f00000   00008000  00000000  00008000  RW  
  SHRAM                 0c000000   00400000  0038a600  00075a00  RWIX
  CORE0_DDR3            80000000   01000000  001dc8dc  00e23724  RWIX
  CORE1_DDR3            81000000   01000000  00000000  01000000  RWIX
  CORE2_DDR3            82000000   01000000  00000000  01000000  RWIX
  CORE3_DDR3            83000000   01000000  00000000  01000000  RWIX
  CORE4_DDR3            84000000   01000000  00000000  01000000  RWIX
  CORE5_DDR3            85000000   01000000  00000000  01000000  RWIX
  CORE6_DDR3            86000000   01000000  00000000  01000000  RWIX
  CORE7_DDR3            87000000   01000000  00000000  01000000  RWIX
  DDR3                  88000000   08000000  00140348  07ebfcb8  RWIX
  DDR3_IPC              90000000   60000000  08000000  58000000  RWIX
  DDR3_HLNK             f0000000   10000000  00000000  10000000  RWIX

5. This works good. 

6. Now I try to move all definitions to platform. For example I try to move DDR3.

MEMORY {
//	L2SRAM:		Defined in platform
//	L1PSRAM:	Defined in platform
//	L1DSRAM:	Defined in platform

    SHRAM:           o = 0x0C000000 l = 0x00400000   /* 4MB Multicore shared Memory */

    CORE0_DDR3:      o = 0x80000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE0 */
    CORE1_DDR3:      o = 0x81000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE1 */
    CORE2_DDR3:      o = 0x82000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE2 */
    CORE3_DDR3:      o = 0x83000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE3 */
    CORE4_DDR3:      o = 0x84000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE4 */
    CORE5_DDR3:      o = 0x85000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE5 */
    CORE6_DDR3:      o = 0x86000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE6 */
    CORE7_DDR3:      o = 0x87000000 l = 0x01000000   /* 32MB DDR3 SDRAM for CORE7 */
//    DDR3:			 o = 0x88000000 l = 0x08000000   /* Shared DDR3 */
    DDR3_IPC:		 o = 0x90000000 l = 0x60000000   /* Shared DDR3 used by shared region */
    DDR3_HLNK:		 o = 0xF0000000 l = 0x10000000   /* 256MB hyperlink window in DDR3 */
}

7. And create a row in platform. I forgot to mention: platform is custom based on evm6678. But this is not issue I suppose because there are not anything crucial I can define there, only memory regions and frequency.

8. Builds OK

******************************************************************************
               TMS320C6x Linker Unix v8.0.1                    
******************************************************************************
>> Linked Wed Mar 25 14:12:41 2015

OUTPUT FILE NAME:   <very_good_project.out>
ENTRY POINT SYMBOL: "_c_int00"  address: 0087e800


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  L2SRAM                00800000   00080000  0007e4ee  00001b12  RW X
  L1PSRAM               00e00000   00008000  00000000  00008000  RW X
  L1DSRAM               00f00000   00008000  00000000  00008000  RW  
  SHRAM                 0c000000   00400000  0038a600  00075a00  RWIX
  CORE0_DDR3            80000000   01000000  001dc8dc  00e23724  RWIX
  CORE1_DDR3            81000000   01000000  00000000  01000000  RWIX
  CORE2_DDR3            82000000   01000000  00000000  01000000  RWIX
  CORE3_DDR3            83000000   01000000  00000000  01000000  RWIX
  CORE4_DDR3            84000000   01000000  00000000  01000000  RWIX
  CORE5_DDR3            85000000   01000000  00000000  01000000  RWIX
  CORE6_DDR3            86000000   01000000  00000000  01000000  RWIX
  CORE7_DDR3            87000000   01000000  00000000  01000000  RWIX
  DDR3                  88000000   08000000  00140348  07ebfcb8  RW X
  DDR3_IPC              90000000   60000000  08000000  58000000  RWIX
  DDR3_HLNK             f0000000   10000000  00000000  10000000  RWIX

the rest of memory map file is similar to stage 4. Checked with diff utility.

9. Let's run this. I have TMDSEVM6678LE with XDS560v2 mezzanine board. I click debug, do System reset, run the program on core0.

Program even not going to run to main, it stucks at ti_sysbios_family_c64p_Hwi_int0. Strange. Restart/Reset/SystemReset  don't help.

I can't say this issue is critical but it would be better to move all memory definitions to one place and later I can use platform definitions in RTSC config which can not be used if defined in .cmd file.

I have been investigated this issue a bit more.

Above situation took place in Release configuration of project. I switched to Debug and program ran. So here is the first statement we can make:

1. There are some flags in project build configuration that interfere with the method of memory placement: platform wizard or .cmd file.

But however program did not run far - it stuck in one of initialization functions. Autopsy has shown that

2. Caching of DDR3 memory into L1 somehow is enabled when we locate "DDR3" memory region by creating a row in Platform Edit.

Of course the obvious decision helped:

var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
	Cache.setMarMeta(0x80000000, 0x80000000, 0);

Now in Debug profile with memories defined only in platform config my program works well. The question is what flag in Release profile breaks execution.