Hi,
The DMCCTL register for the C6457's DDR2 perhipheral is listed on pg.48 of sprugk5b as having the structure:
But, on pg.37, the description mentions an IFRESET bit, which is nowhere to be found, except on the C6455.
It looks just like a leftover from the C6455's datasheet, except that the GEL file for my C6457 EVM board contains a line which clearly actuates IFRESET. So I'm confused -- which is correct? Could a TI employee please comment?
I'd also like to ask about general setup for the DDR2 module. Here's what I have so far (executed in this order):
- SDCFG: set NM, CL, IBANK, PAGESIZE, TIMUNLOCK, and BOOT_UNLOCK (this register has RSV bits which must be unchanged)
- SDRFC: set refresh rate (this register has RSV bits which must be unchanged)
- *** Question: what are these RSV values? The datasheet omits the default field! ***
- SDTIM1: set timings 1
- SDTIM2: set timings 2
- DMCCTL: set PVTCNTL, RL (this register has RSV bits which must be unchanged)
- SDCFG: set DDQS, DDR2_ENABLE, DDR_ENABLE, SDRAM_ENABLE while holding other settings
- *** Question: should BOOT_UNLOCK be kept high at this point? How about TIMUNLOCK? ***
I ask the last because the EVM GEL file brings BOOT_UNLOCK low at the same time it sets the 4 enables, while leaving TIMUNLOCK high. The next line lowers TIMUNLOCK. I wonder if this would create a race condition between how BOOT_UNLOCK propagates and the 4 enables?
Thanks!
- Craig