Problem of Memory Write PCIe transaction troughtput performances EDMA3 (SYS/BIOS ) Vs EDMA3(CSL)

EDMA3_DRV_Result edma3_Transfert(EDMA3_DRV_Handle hEdma, UINT32 acnt, UINT32 bcnt,
		UINT32 ccnt, UINT32* _srcBuff1, UINT32* _dstBuff1,
		EDMA3_DRV_SyncType syncType) {

	EDMA3_DRV_Result result = EDMA3_DRV_SOK;
	EDMA3_DRV_PaRAMRegs paramSet = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
	UINT32 chId = 0;
	UINT32 tcc = 0;
	INT32 i;
	UINT32 Istestpassed = 0u;
	UINT32 numenabled = 0;
	UINT32 BRCnt = 0;
	INT32 srcbidx = 0, desbidx = 0;
	INT32 srccidx = 0, descidx = 0;

#ifdef EDMA3_ENABLE_DCACHE

#endif  /* EDMA3_ENABLE_DCACHE */

	/* Set B count reload as B count. */
	BRCnt = bcnt;

	/* Setting up the SRC/DES Index */
	srcbidx = (INT32) acnt;
	desbidx = (INT32) acnt;
	if (syncType == EDMA3_DRV_SYNC_A) {
		/* A Sync Transfer Mode */
		srccidx = (INT32) acnt;
		descidx = (INT32) acnt;
	} else {
		/* AB Sync Transfer Mode */
		srccidx = ((INT32) acnt * (INT32) bcnt);
		descidx = ((INT32) acnt * (INT32) bcnt);
	}

	/* Setup for Channel 1*/
	tcc = EDMA3_DRV_TCC_ANY;
	chId = EDMA3_DRV_DMA_CHANNEL_ANY;

	/* Request any DMA channel and any TCC */
	if (result == EDMA3_DRV_SOK) {
		result = EDMA3_DRV_requestChannel(hEdma, &chId, &tcc,
				(EDMA3_RM_EventQueue) 0, &callback1, NULL);
	}

	if (result == EDMA3_DRV_SOK) {
		/* Fill the PaRAM Set with transfer specific information */

		paramSet.srcAddr = (UINT32) (_srcBuff1);
		paramSet.destAddr = (UINT32) (_dstBuff1);

		/**
		 * Be Careful !!!
		 * Valid values for SRCBIDX/DSTBIDX are between �32768 and 32767
		 * Valid values for SRCCIDX/DSTCIDX are between �32768 and 32767
		 */
		paramSet.srcBIdx = srcbidx;
		paramSet.destBIdx = desbidx;
		paramSet.srcCIdx = srccidx;
		paramSet.destCIdx = descidx;

		/**
		 * Be Careful !!!
		 * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
		 * ACNT/BCNT/CCNT must be greater than or equal to 1.
		 * Maximum number of bytes in an array (ACNT) is 65535 bytes
		 * Maximum number of arrays in a frame (BCNT) is 65535
		 * Maximum number of frames in a block (CCNT) is 65535
		 */
		paramSet.aCnt = acnt;
		paramSet.bCnt = bcnt;
		paramSet.cCnt = ccnt;

		/* For AB-synchronized transfers, BCNTRLD is not used. */
		paramSet.bCntReload = BRCnt;

		paramSet.linkAddr = 0xFFFFu;

		/* Src & Dest are in INCR modes */
		paramSet.opt &= 0xFFFFFFFCu;
		/* Program the TCC */
		paramSet.opt |= ((tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK);

		/* Enable Intermediate & Final transfer completion interrupt */
		paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);
		paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);

		if (syncType == EDMA3_DRV_SYNC_A) {
			paramSet.opt &= 0xFFFFFFFBu;
		} else {
			/* AB Sync Transfer Mode */
			paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
		}

		/* Now, write the PaRAM Set. */
		result = EDMA3_DRV_setPaRAM(hEdma, chId, &paramSet);
	}
	if (result == EDMA3_DRV_SOK) {
		/*Need to activate next param*/
		if (syncType == EDMA3_DRV_SYNC_A) {
			numenabled = bcnt * ccnt;
		} else {
			/* AB Sync Transfer Mode */
			numenabled = 20;
		}
											/***********Timer begin********/
											  Nbefore = Timestamp_get32();
											/******************************/
		for (i = 0; i < numenabled; i++) {

			irqRaised1 = 0;


			/*
			 * Now enable the transfer as many times as calculated above.
			 */


			result = EDMA3_DRV_enableTransfer(hEdma, chId,EDMA3_DRV_TRIG_MODE_MANUAL);

			if (result != EDMA3_DRV_SOK) {
				printf("edma3_test: EDMA3_DRV_enableTransfer "
						"Failed, error code: %d\r\n", result);
				break;
			}


			/* Wait for the Completion ISR. */
			while (irqRaised1 == 0u) {
				/* Wait for the Completion ISR. */
				printf("waiting for interrupt...\n");
			}

			/* Check the status of the completed transfer */
			if (irqRaised1 < 0) {
				/* Some error occured, break from the FOR loop. */
				printf("\r\nedma3_test: Event Miss Occured!!!\r\n");

				/* Clear the error bits first */
				result = EDMA3_DRV_clearErrorBits(hEdma, chId);
				break;
			}

		}
								/*********************Timer end***********************/
								              Nafter = Timestamp_get32();
								/*****************************************************/
								
											/******Number of cycle********/
											edma_value = (Nafter - Nbefore);

	}

	/* Match the Source and Destination Buffers. */
	if (EDMA3_DRV_SOK == result) {
		 for (i = 0; i < acnt * bcnt * ccnt; i++) {
		 if (_srcBuff1[i] != _dstBuff1[i]) {
		 Istestpassed = 0u;
		 printf("edma3_test: Data write-read matching"
		 "FAILED at i = %d\r\n", i);
		 break;
		 }
		 }
	
		Istestpassed = 1u;
		if (i == acnt * bcnt * ccnt) {
		 Istestpassed = 1u;
		 }
	
		/* Free the previously allocated channel. */
		result = EDMA3_DRV_freeChannel(hEdma, chId);
		if (result != EDMA3_DRV_SOK) {
			printf("edma3_test: EDMA3_DRV_freeChannel() FAILED, "
					"error code: %d\r\n", result);
		}
	}

	if (Istestpassed == 1u) {
			printf("edma3_test PASSED\r\n");
	} else {
		printf("edma3_test FAILED\r\n");
		result =
				((EDMA3_DRV_SOK == result) ? EDMA3_DATA_MISMATCH_ERROR : result);
	}

	return result;
}