6748 Configuration and Power Consumption

Thomas Price7137

Other Parts Discussed in Thread: OMAPL138

I am supposed to get a review of the PWRM interface from TI later this week so I'm trying not to necessarily get into the details of this interface yet.

Basically I have been trying to modify the gel file to reduce the processor and memory speed and to turn off all the non-relevant peripherals. However I'm not seeing it make any difference in my power measurements. I have pasted my gel file changes below and I imagine I am fundamentally doing something wrong if I'm not seeing a difference. Does anyone else know any tricks to turning off the peripherals right through the gel and to slow down the processor? Any other considerations when using the 6748 SOM?

I'm using the 6748 SOM and have modified the gel file for the C6748.gel in the following way:

OnTargetConnect( )
{
    Clear_Memory_Map();
    Setup_Memory_Map();
    //PSC_All_On_Experimenter(); //original
    //Core_300MHz_mDDR_132MHz(); //original

PSC_Power_Special(); //Power Test TP
Core_100MHz_mDDR_102MHz(); //Power Test TP

PINMUX0 = 0x44440000; //Uart1 + Uart2
PINMUX1 = 0x00000000;
PINMUX2 = 0x00000000;
PINMUX3 = 0x00000000;
PINMUX4 = 0x22220000; //Uart1 + Uart2
PINMUX5 = 0x11000000; //EMIFA + EMIFB
PINMUX6 = 0x11111111; //EMIFA + EMIFB
PINMUX7 = 0x11111111; //EMIFA + EMIFB
PINMUX8 = 0x11111111; //EMIFA + EMIFB
PINMUX9 = 0x11111111; //EMIFA + EMIFB
PINMUX10 = 0x11111111; //EMIFA + EMIFB
PINMUX11 = 0x11111111; //EMIFA + EMIFB
PINMUX12 = 0x11111111; //EMIFA + EMIFB
PINMUX13 = 0x00000000;
PINMUX14 = 0x00000000;
PINMUX15 = 0x00000000;
PINMUX16 = 0x00000000;
PINMUX17 = 0x00000000;
PINMUX18 = 0x00000000;
PINMUX19 = 0x00000000;
//PINMUX0 = 0x44000000; //Spi0 + Uart2
//PINMUX4 = 0x00220011; //Spi0 + Uart2
//PINMUX3 = 0x11111111; //Spi0 + Uart2
}

hotmenu PSC_Power_Special() {
    GEL_TextOut("\tEnabling Only Relevant PSCs...\n","Output",1,1,1);
    // PSC0
    PSC0_LPSC_enable(0, LPSC_EDMA_CC0);
    PSC0_LPSC_enable(0, LPSC_EDMA_TC0);
    PSC0_LPSC_enable(0, LPSC_EDMA_TC1);
    //PSC0_LPSC_disable(0, LPSC_SPI0);
    //PSC0_LPSC_disable(0, LPSC_MMCSD0);
    //PSC0_LPSC_disable(0, LPSC_UART0);
    //PSC0_LPSC_enable(0, LPSC_SCR0);
    //PSC0_LPSC_enable(0, LPSC_SCR1);
    //PSC0_LPSC_enable(0, LPSC_SCR2);

    // PSC1
    PSC1_LPSC_enable(0, LPSC_EDMA_CC1);
    //PSC1_LPSC_disable(0, LPSC_USB20);
    //PSC1_LPSC_disable(0, LPSC_USB11);
    //CFGCHIP2 = 0x09F2; //Enable USB clock, PHY_PLLON, glue logic mux(USB2 ref clk input)
    //PSC1_LPSC_disable(0, LPSC_GPIO);
    //PSC1_LPSC_enable(0, LPSC_UHPI);
    //PSC1_LPSC_enable(0, LPSC_EMAC);
    PSC1_LPSC_enable(0, LPSC_DDR);
    //PSC1_LPSC_disable(0, LPSC_MCASP0);
    //PSC1_LPSC_force(LPSC_SATA);
    //PSC1_LPSC_disable(0, LPSC_SATA);
    //PSC1_LPSC_disable(0, LPSC_SPI1);
    //PSC1_LPSC_disable(0, LPSC_I2C1);
    PSC1_LPSC_enable(0, LPSC_UART1);
    PSC1_LPSC_enable(0, LPSC_UART2);
    //PSC1_LPSC_disable(0, LPSC_MCBSP0);
    //PSC1_LPSC_disable(0, LPSC_MCBSP1);
    PSC1_LPSC_enable(0, LPSC_EPWM);
    PSC1_LPSC_enable(0, LPSC_MMCSD1);
    PSC1_LPSC_enable(0, LPSC_ECAP);
    PSC1_LPSC_enable(0, LPSC_EDMA_TC2);
    //PSC1_LPSC_enable(0, LPSC_SCR_F0);
    //PSC1_LPSC_enable(0, LPSC_SCR_F1);
    //PSC1_LPSC_enable(0, LPSC_SCR_F2);
    //PSC1_LPSC_enable(0, LPSC_SCR_F6);
    //PSC1_LPSC_enable(0, LPSC_SCR_F7);
    //PSC1_LPSC_enable(0, LPSC_SCR_F8);
    PSC1_LPSC_enable(0, LPSC_BR_F7);
    PSC1_LPSC_enable(0, LPSC_SHARED_RAM);

GEL_TextOut("\tPSC Enable Complete.\n","Output",1,1,1);
GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

over 15 years ago

0 tlee over 15 years ago

TI__Guru 62975 points

Thomas,

How are you measuring the power on the device? It can be fairly tricky to get a true measurment of C6748 power consumption on the SOM.

-Tommy

0 Thomas Price7137 over 15 years ago in reply to tlee

Intellectual 625 points

Tommy-

The SOM is plugged into a custom base board we have created. This base board has built in a Test Point which measures the voltage drop across a 1 ohm resistor feeding the +5V pins 90, 92,96, and 98 on the SOM.

-Thomas

0 Mukul Bhatnagar over 15 years ago in reply to Thomas Price7137

TI__Guru* 83705 points

Hi Thomas

Measuring at 5V_IN is not going to give you a good handle on power consumption and power savings on the OMAPL138/C6748. FYI the PMIC on the SOM supplies to a lot of on board components on the SOM apart from the OMAPL138/C6748 device.

Also there is a reasonable power draw/dissipation going from 5V IN to LDO1/LDO2 which are sourcing low current/voltage etc.

The steps that you are trying to do in the gel file will essentially impact device clocking and peripheral clocking. You would be running the device at a lower speed and have peripherals clock gated , and the most impact of the power savings for that will show up on the device CVDD rail (core clocking power), so you should really be analyzing the DCDC3 output of the PMIC.

The SOM might not be very conducive to being able to directly hook up a volt meter to a tap point, but you could arguable blue wire at R90 (in the bottom side of the SOM , near the single connector) to guage the true power savings on core.

Some of the IO supplies are going to be dependent not only on the state of pull up/pull downs of the device, but also the state of all the other on board components that you see being sourced by the PMIC (highlighted in red in the rough list below)

Here is a rough list

VDCDC1 (3.3V)
OMAPL138/C6748 I/O (VDD33_USB1, VDDA33_USB0)
Serial Boot Flash
10/100 Ethernet PHY (3.3V analog port power)
LVDS Clock Generator (CDCM chip)
Misc Ics (Voltage translation, buffers, etc), Pullups

VDCDC2:1.8V/3.3V
OMAPL138/C6748 I/O (DVDD3318A, DVDD3318B, DVDD3318C)
OMAPL138 Baseboard Components
10/100 Ethernet PHY (1.6V to 3.3V I/O pad power)
Misc Ics
Pull Ups

VDCDC3 :1.2 Variable
OMAPL138/C6748 CVDD

VLDO2:1.2V LDO
OMAPL138/C6748
PLLs (VDDA12_PLL1, VDDA12_PLL0), RVDD
SATA core (VDD3, SATA_VDDA, SATA_VDDD),
USB core (USB_CVDD)
# 10/100 Ethernet PHY (1.2V core voltage)

VLDO3 :1.8V LDO
OMAPL138 : SATA_VDDR, VDDA18_USB0, VDDA18_USB1, VDD18V, DDR_DVDD18
mDDR: 1Gbit Mobile DDR

0 clam over 15 years ago in reply to Mukul Bhatnagar

TI__Expert 8785 points

Thomas,

Another way to obtain the lowest power state is by using deepsleep. Below, you can find sample code to configure and put the device in deepsleep. The RTC will take the device out of deepsleep after 15 seconds. The sample code assumes the device is in the default (out-of-reset) state.

- Christina

#define PDCCMD_REG *(Uint32 volatile *)0x01810000

/*PLL0 Controller Control Register */
#define PLL0_BASE_ADDR    0x01C11000
#define PLL0_PLLCTL        (PLL0_BASE_ADDR + 0x100)    /*PLL Control Register*/
#define PLL0_OCSEL        (PLL0_BASE_ADDR + 0x104)    /*OBSCLK Select Register*/
#define PLL0_SECCTL        (PLL0_BASE_ADDR + 0x108)    /*PLL Secondary Control Register*/
#define PLL0_PLLM        (PLL0_BASE_ADDR + 0x110)    /*PLL Multiplier Control Register*/
#define PLL0_PREDIV        (PLL0_BASE_ADDR + 0x114)    /*PLL Pre-Divider control Register*/
#define PLL0_PLLDIV1    (PLL0_BASE_ADDR + 0x118)    /*PLL Controller Div1 Register*/
#define PLL0_PLLDIV2    (PLL0_BASE_ADDR + 0x11C)    /*PLL Controller Div2 Register*/
#define PLL0_PLLDIV3    (PLL0_BASE_ADDR + 0x120)    /*PLL Controller Div3 Register*/
#define PLL0_OSCDIV1    (PLL0_BASE_ADDR + 0x124)    /*Oscilator Divider Register*/
#define PLL0_POSTDIV    (PLL0_BASE_ADDR + 0x128)    /*PLL Post-Divider Register*/
#define PLL0_BPDIV        (PLL0_BASE_ADDR + 0x12C)    /*Bypass Divider Register*/
#define PLL0_WAKEUP        (PLL0_BASE_ADDR + 0x130)    /*Wakeup Register*/
#define PLL0_PLLCMD        (PLL0_BASE_ADDR + 0x138)    /*PLL Controller Command Register*/
#define PLL0_PLLSTAT    (PLL0_BASE_ADDR + 0x13C)    /*PLL Controller Status Register*/
#define PLL0_ALNCTL        (PLL0_BASE_ADDR + 0x140)    /*PLL Controller Clock Align Control Register*/
#define PLL0_DCHANGE    (PLL0_BASE_ADDR + 0x144)    /*PLLDiv Ratio Change status Register*/
#define PLL0_CKEN        (PLL0_BASE_ADDR + 0x148)    /*Clock Enable Control Register*/
#define PLL0_CKSTAT        (PLL0_BASE_ADDR + 0x14C)    /*Clock Status Register*/
#define PLL0_SYSTAT        (PLL0_BASE_ADDR + 0x150)    /*SYSCLK Status Register*/
#define PLL0_PLLDIV4    (PLL0_BASE_ADDR + 0x160)    /*PLL Controller Div4 Register*/
#define PLL0_PLLDIV5    (PLL0_BASE_ADDR + 0x164)    /*PLL Controller Div5 Register*/
#define PLL0_PLLDIV6    (PLL0_BASE_ADDR + 0x168)    /*PLL Controller Div6 Register*/
#define PLL0_PLLDIV7    (PLL0_BASE_ADDR + 0x16C)    /*PLL Controller Div7 Register*/
#define PLL0_PLLDIV8    (PLL0_BASE_ADDR + 0x170)    /*PLL Controller Div8 Register*/
#define PLL0_PLLDIV9    (PLL0_BASE_ADDR + 0x174)    /*PLL Controller Div8 Register*/

/*PLL1 Controller Control Register */
#define PLL1_BASE_ADDR    0x01E1A000
#define PLL1_PLLCTL        (PLL1_BASE_ADDR + 0x100)    /*PLL Control Register*/
#define PLL1_OCSEL        (PLL1_BASE_ADDR + 0x104)    /*OBSCLK Select Register*/
#define PLL1_SECCTL        (PLL1_BASE_ADDR + 0x108)    /*PLL Secondary Control Register*/
#define PLL1_PLLM        (PLL1_BASE_ADDR + 0x110)    /*PLL Multiplier Control Register*/
#define PLL1_PREDIV        (PLL1_BASE_ADDR + 0x114)    /*PLL Pre-Divider control Register*/
#define PLL1_PLLDIV1    (PLL1_BASE_ADDR + 0x118)    /*PLL Controller Div1 Register*/
#define PLL1_PLLDIV2    (PLL1_BASE_ADDR + 0x11C)    /*PLL Controller Div2 Register*/
#define PLL1_PLLDIV3    (PLL1_BASE_ADDR + 0x120)    /*PLL Controller Div3 Register*/
#define PLL1_OSCDIV1    (PLL1_BASE_ADDR + 0x124)    /*Oscilator Divider Register*/
#define PLL1_POSTDIV    (PLL1_BASE_ADDR + 0x128)    /*PLL Post-Divider Register*/
#define PLL1_BPDIV        (PLL1_BASE_ADDR + 0x12C)    /*Bypass Divider Register*/
#define PLL1_WAKEUP        (PLL1_BASE_ADDR + 0x130)    /*Wakeup Register*/
#define PLL1_PLLCMD        (PLL1_BASE_ADDR + 0x138)    /*PLL Controller Command Register*/
#define PLL1_PLLSTAT    (PLL1_BASE_ADDR + 0x13C)    /*PLL Controller Status Register*/
#define PLL1_ALNCTL        (PLL1_BASE_ADDR + 0x140)    /*PLL Controller Clock Align Control Register*/
#define PLL1_DCHANGE    (PLL1_BASE_ADDR + 0x144)    /*PLLDiv Ratio Change status Register*/
#define PLL1_CKEN        (PLL1_BASE_ADDR + 0x148)    /*Clock Enable Control Register*/
#define PLL1_CKSTAT        (PLL1_BASE_ADDR + 0x14C)    /*Clock Status Register*/
#define PLL1_SYSTAT        (PLL1_BASE_ADDR + 0x150)    /*SYSCLK Status Register*/
#define PLL1_PLLDIV4    (PLL1_BASE_ADDR + 0x160)    /*PLL Controller Div4 Register*/
#define PLL1_PLLDIV5    (PLL1_BASE_ADDR + 0x164)    /*PLL Controller Div5 Register*/
#define PLL1_PLLDIV6    (PLL1_BASE_ADDR + 0x168)    /*PLL Controller Div6 Register*/
#define PLL1_PLLDIV7    (PLL1_BASE_ADDR + 0x16C)    /*PLL Controller Div7 Register*/
#define PLL1_PLLDIV8    (PLL1_BASE_ADDR + 0x170)    /*PLL Controller Div8 Register*/
#define PLL1_PLLDIV9    (PLL1_BASE_ADDR + 0x174)    /*PLL Controller Div8 Register*/

/*SYSCFG0 Register */
#define SYSCFG0_BASE_ADDR 0x01C14000
#define SYSCFG0_KICK0   (SYSCFG0_BASE_ADDR + 0x38) /*KICK0 register*/
#define SYSCFG0_KICK1   (SYSCFG0_BASE_ADDR + 0x3C)    /*KICK1 register*/
#define SYSCFG0_PINMUX0 (SYSCFG0_BASE_ADDR + 0x120)    /*PINMUX0 register*/

/*SYSCFG1 Register */
#define SYSCFG1_BASE_ADDR 0x01E2C000
#define SYSCFG1_DDRSLEW   (SYSCFG1_BASE_ADDR + 0x04)
#define SYSCFG1_DEEPSLEEP (SYSCFG1_BASE_ADDR + 0x08)
#define SYSCFG1_PUPDEN    (SYSCFG1_BASE_ADDR + 0x0C)
#define SYSCFG1_PUPDSEL   (SYSCFG1_BASE_ADDR + 0x10)
#define SYSCFG1_RXACTIVE (SYSCFG1_BASE_ADDR + 0x14)

/*RTC Register */
#define RTC_BASE_ADDR   0x01C23000
#define RTC_SECOND     (RTC_BASE_ADDR + 0x00)
#define RTC_MINUTE       (RTC_BASE_ADDR + 0x04)
#define RTC_HOUR           (RTC_BASE_ADDR + 0x08)
#define RTC_DAY            (RTC_BASE_ADDR + 0x0C)
#define RTC_MONTH            (RTC_BASE_ADDR + 0x10)
#define RTC_YEAR            (RTC_BASE_ADDR + 0x14)
#define RTC_DOTW            (RTC_BASE_ADDR + 0x18)
#define RTC_ALMSEC     (RTC_BASE_ADDR + 0x20)
#define RTC_CTRL        (RTC_BASE_ADDR + 0x40)
#define RTC_STATUS     (RTC_BASE_ADDR + 0x44)
#define RTC_INTR        (RTC_BASE_ADDR + 0x48)
#define RTC_OSC            (RTC_BASE_ADDR + 0x54)
#define RTC_KICK0R        (RTC_BASE_ADDR + 0x6C)
#define RTC_KICK1R        (RTC_BASE_ADDR + 0x70)

/*TIMER Register */
#define TMR_BASE_ADDR   0x01C20000
#define TMR_TIM12         (TMR_BASE_ADDR + 0x10)
#define TMR_PRD12         (TMR_BASE_ADDR + 0x18)
#define TMR_TCR         (TMR_BASE_ADDR + 0x20)
#define TMR_TGCR         (TMR_BASE_ADDR + 0x24)

/*Extra variables */
#define RTC_RESET_TIME    2288

unsigned int main()
{
    unsigned int counter;

    // Set DDR I/O receivers to LVCMOS mode
    *(unsigned int*) SYSCFG1_DDRSLEW = *(unsigned int*) SYSCFG1_DDRSLEW | 0x0010; //LVCMOS receiver

    /**** CONFIGURING DEEPSLEEP ****/
    //1. DDR2/mDDR should be clock gated
    //   --No configuration needed. Default clock gated

    //2. SATA PHY should be disabled
    //   --No configuration needed. Default disabled

    //3. USB2.0 PHY should be disabled
    //   --No configuration needed. Default disabled

    //4. USB1.1 PHY should be disabled
    //   --No configuration needed. Default disabled

    //5. PLLs should be placed in bypass mode (clear PLLEN bit in PLLCTL register)
    //   --No configuration needed. Default in bypass mode

    //6. PLLs should be powered down (set PLLPWRDN bit in PLLCTL register)
    //   --No configuration needed. Default powered down

    //7. Configure the desired wake-up time as an alarm in RTC
    *(unsigned int*) TMR_TIM12    = 0x00000000;
    *(unsigned int*) TMR_PRD12    = 0xFFFFFFFF;
    *(unsigned int*) TMR_TGCR    = (*(unsigned int*) TMR_TGCR & ~0x000C) | 0x0004; // Dual, unchained mode
    *(unsigned int*) TMR_TGCR    = (*(unsigned int*) TMR_TGCR & ~0x0001) | 0x0001; // Not in reset
    *(unsigned int*) TMR_TCR    = (*(unsigned int*) TMR_TCR & ~0x00C0) | 0x0080; // Enabled continuously

    *(unsigned int*) RTC_KICK0R = 0x83E70B13;                                //Unlock RTC registers
    *(unsigned int*) RTC_KICK1R = 0x95A4F1E0;

    *(unsigned int*) RTC_OSC    = (*(unsigned int*) RTC_OSC & ~0x0020) | 0x0020; // Software reset
    counter = *(unsigned int*) TMR_TIM12 + RTC_RESET_TIME;
    while( *(unsigned int*) TMR_TIM12 < counter ){}

    *(unsigned int*) RTC_ALMSEC = *(unsigned int*) RTC_ALMSEC | 0x0015;     //Set the alarm (15 seconds)
    *(unsigned int*) RTC_INTR     = *(unsigned int*) RTC_INTR   | 0x0008;     //Enable Alarm

    *(unsigned int*) RTC_CTRL     = *(unsigned int*) RTC_CTRL   | 0x0081;        //Enable split power and start RTC

    //while((*(unsigned int*) RTC_STATUS & 0x0040) == 0){} // Extra code to test the alarm

    //8. Configure PINMUX0_31_28 as output of RTC_ALARM.
    *(unsigned int*) SYSCFG0_KICK0 = 0x83E70B13;
    *(unsigned int*) SYSCFG0_KICK1 = 0x95A4F1E0;
    *(unsigned int*) SYSCFG0_PINMUX0 = *(unsigned int*) SYSCFG0_PINMUX0 & ~0xF0000000;
    *(unsigned int*) SYSCFG0_PINMUX0 = *(unsigned int*) SYSCFG0_PINMUX0 | 0x20000000;

    //9. Configure the desired delay in SLEEPCOUNT
    *(unsigned int*) SYSCFG1_DEEPSLEEP = *(unsigned int*) SYSCFG1_DEEPSLEEP & ~0xFFFF; // Set sleepcount to 0

    //10. Set the SLEEPENABLE bit in DEEPSLEEP. Automatically clears the SLEEPCOMPLETE bit.
    *(unsigned int*) SYSCFG1_DEEPSLEEP = *(unsigned int*) SYSCFG1_DEEPSLEEP | 0x80000000; // Enable deepsleep

    //11. Begin polling SLEEPCOMPLETE until it is set to 1 (set once device is woken up)
    while((*(unsigned int*) SYSCFG1_DEEPSLEEP & 0x40000000) == 0){}        // Wait for the device to come out of deepsleep

    //12. Clear the SLEEPENABLE bit in DEEPSLEEP
    *(unsigned int*) SYSCFG1_DEEPSLEEP = *(unsigned int*) SYSCFG1_DEEPSLEEP & ~0x80000000;    // Disable deepsleep

       asm(" IDLE");

    //should never reach here
    return (1);
}

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6748 Configuration and Power Consumption