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C66x Cache Coherency Problem

Alphan Karacaer56
Intellectual 835 points

Hello,

We are having an absurd problem about Cache Coherency in C66x DSP Cores.

DSP Core writes to Internal Memory and FFTC reads from the same address, According to Cache UG L1D and L2 SRAM are cache coherent thus no need for cache writeback.

But when reading from Memory Browser, L1D is different from L2.

Is this possible or are we missing somthing?

  • 0
    TI__Mastermind 30825 points
    The statement in the Cache UG regarding Coherence is:

    C66x DSPs automatically maintain cache coherence for data accesses by the CORE and
    EDMA/IDMA through a hardware cache coherence protocol based on snoop
    commands. The coherence mechanism is activated on a DMA read and write access.
    When a DMA read of a cached L2 SRAM location occurs, the data is directly forwarded
    from L1D cache to the DMA without being updated in L2 SRAM. On a DMA write, the
    data is forwarded to L1D cache and is updated in L2 SRAM.

    This means that the CorePac and EDMA/IDMA transfers to and from it remain coherent.

    I'm not sure how the FFTC is accessing it. If you're using EDMA then it would be coherent.

    That said, the updates by the CorePac to the data in L2 that has been cached into L1D are going to be written into L1D and not directly to L2. Only when the L1D is evicted, a writeback is commanded, or an access by EDMA/IDMA to the L2 location occurs is that data going to be physically written back to L2 space.

    And thus, when looking at the specific memory locations w/ the various cache levels, you will often seen the data cached in L1D for the location in L2 memory space.

    Best Regards,
    Chad
  • 0 in reply to Chad Courtney
    Intellectual 835 points

    Thank you for the reply.

    I was confused because when we read related address from another core's point of view in memory browser, we also see L1D data, same applies for the physical memory view. 

    So we should do cache wb and inv operations.

    Thanks a lot.