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Few doubts on EDMA and EMIF16 data transfer

Nagi Reddy chitta
Prodigy 220 points

Dear E2E,

We are designing networking product using "Keystone 66AK2E02".

Basically we are planning to use EMIF16 interface (usually meant for Flash) for interfacing the Keystone processor (EMIF16 interface) to our one of  our own chip via an FPGA. Couple of questions w.r.t. this:

1. Does EDMA allow direct transfer between EMIF16 and DDR? If so how? If not DDR, which is the landing area for the data from EMIF16?

2. We want to use one EDMA channel for read from EMIF16 (data from SL100X via FPGA) and a separate channel for write to EMIF16 (data for our IC via FPGA). How will the two EDMA channels interleave their accesses – is it at DMA block boundary? If there is a stall on EMIF16 say read EDMA channel (maybe at a DMA block boundary), is it allowed to shift to an EMIF16 write EDMA channel?

Any pointers would be really helpful.

Best Regards,

Nagi

  • 0
    TI__Mastermind 43660 points
    Hello Nagi,

    We are working on this post and get back to you. Thank you for your patience.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 220 points
    Thanks Senthil.

    Would be really helpful if you can get me the answers for my post at the earliest.
    I am going thru the technical reference manual of this silicon, but not getting enough data w.r.t using EDMA for EMIF16 interface, hence the request to TI for clarifications.

    Best Regards,
    Nagi
  • 0
    TI__Mastermind 35645 points

    Hi Nagi,

    Thanks for your post.

    To address #1, No issues, obviously EDMA would allow direct transfer between EMIF16 and DDR2 and the landing area can be any RAM (L2RAM, shared RAM, SDRAM, anyinternal memory etc.)

    To address #2, since you are using two DMA channels, one for read from EMIF16 and the other for write to EMIF16, there shouldn't be any space for DMA block, may be stall which is agreed and the EDMA CC will execute each event based on priority basis on the DMA channel queues and the queue priority register (QUEPRI) allows you to change the priority of the individual queues and the priority of the transfer request (TR) associated with the events queued in the queue. For more details, please refer EDMA3 user guide for EDMA prioritization and kindly refer sections 2.14 & 4.2.1.8

    http://www.ti.com/lit/ug/sprugs5a/sprugs5a.pdf

    Thanks & regards,

    Sivaraj K

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