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TMS320C6457 DDR2 Implementation Guidelines

Ken Delmage
Prodigy 80 points
Other Parts Discussed in Thread: TMS320C6457

I need to know how important it is to have all bits of a DDR2 byte-lane (including data mask and data strobe signals) routed on the same layer of a PWB?  And, if this is an important aspect of a DDR2 implementation, why doesn't the "TMS320C6457 DDR Implementation Guidelines" (SPRAAG6D-December 2006- Revised January 2010) explicitly state this as a requirement?

The "TMS320C6457 DDR Implementation Guidelines" also does not make any recommendation for the impedance of the differential lines.  It does, however, recommend that all single-ended lines have a nominal characteristic impedance of 50 ohms.  Therefore, is it reasonable to conclude that all differential lines need to have a characteristic impedance of 100 ohms?

  • 0
    TI__Intellectual 1610 points

    Ken Delmage said:

    I need to know how important it is to have all bits of a DDR2 byte-lane (including data mask and data strobe signals) routed on the same layer of a PWB?  And, if this is an important aspect of a DDR2 implementation, why doesn't the "TMS320C6457 DDR Implementation Guidelines" (SPRAAG6D-December 2006- Revised January 2010) explicitly state this as a requirement?

    It's not important, hence the guidelines don't state it as a requirement.

    Ken Delmage said:

    The "TMS320C6457 DDR Implementation Guidelines" also does not make any recommendation for the impedance of the differential lines.  It does, however, recommend that all single-ended lines have a nominal characteristic impedance of 50 ohms.  Therefore, is it reasonable to conclude that all differential lines need to have a characteristic impedance of 100 ohms?

    The guidelines indirectly specify the differential impedance.  Single ended lines are 50 ohms.  The differential lines are to be routed at minimum spacing, which will result in a differential impedance less than 100 ohms.  The concern here is that both differential lines see the same noise, hence the minimum spacing.  Impedance concerns are secondary.

    So, the specific answer to your question is no, it is not reasonable to conclude that all differential lines need to have a characteristic impedance of 100 ohms.

     

    -Mike

     

  • 0 in reply to Michael Shust
    Prodigy 80 points

    Mike,

    Can you please take a moment to explain why it is NOT important to route all data byte-lane signals on the same layer?

  • 0 in reply to Ken Delmage
    TI__Intellectual 1610 points

    Because each routing layer has a corresponding ground reference and there are enough ground vias to allow jumping of return currents between these planes to control crosstalk to a reasonable level.  The guidelines should be looked at on the whole, not in individual parts.  Overall the guidelines are quite restrictive.  In the interest of brevity, not all these restrictions are explicitly pointed out.

    These DDR routing guidelines have been used in basically the same form since 2005 and have a proven track record of functioning reliably.  They are loose enough to allow creative implementation by customers, but strict enough to ensure reliability.

    Why do you think it's important to route them on the same layer?

    -Mike

  • 0 in reply to Michael Shust
    Prodigy 80 points

    Hi Mike,

    Thanks for your help with this question.  I thought your first response was a bit terse, and hence my supplemental question ... just to see how bullish you would be with your own response.

    There are two reasons why I think routing all byte-lane signals on the same layer may be important:

    1) There are other manufacturer's DDR2 Implementaion Guidelines/Checklists, which recommend that all signals within a given byte-lane should be routed on the same "critical" layer (e.g. Freescale AN2910).

    2) We are contracting a consulting group to do our simulations, and their first comment to us was as follows:   "I just overviewed the DDR2 interface routing, and I saw that the Byte-lane group signals have been routed on multiple layers.  A Byte-lane is the 8 bits of a selected byte + the data mask of this byte + the data strobe of this byte.  Usually, you put a Byte-lane on the same layer to minimise the effect of the process variation in PCB fabrication."

    However, perhaps this routing "best practice" is only important when routing out to DIMMs where the trace lengths are longer.  In the TI guidelines, the maximum trace lengths must be kept very short (i.e. < 3.1 inches) presumably because the TI guidelines are for routing between devices which are located on the same board.  So, this may be the reason that the effect of routing a byte lane's signals on different layer may NOT be important as you say.  In our particular case, we have respected all of TI's guidelines so your assertion "it is not important" is valid.  The proviso, however, is that we have observed every other restriction in the TI guidelines to a tee.

    Perhaps you could comment on my "However, ..." response, and on Freescale's application note, and on our consultant's comment, ... just to confirm that we are both on the same page.

    Ken

  • 0 in reply to Ken Delmage
    TI__Intellectual 1610 points

    I did not mean for it to sound terse.  I was trying to be brief and direct and certainly did not mean to offend.

    Like other forms of engineering, SI must be a compromise with other system parameters and goals.  My comments about "not important" only applies to our case and I would not extend it arbitrarily to other systems.  Given our (TI) design decisions, the supplied spec is sufficient to meet timings without being more burdensome to our customers than necessary.  I am a strong proponent of simple, complete specs written for the target audience.  The longer the spec is, the harder it is to follow and the harder it is to verify.

    Yes, we are on the same page :-).

    -Mike

  • 0 in reply to Michael Shust
    Prodigy 80 points

    Mike,

    Glad to hear that we're on the same page!  :o)

    Absolutely no offence taken.  I simply thought your original response needed a little more explanation in order for me, and my peers, to know the background for your response.

    I'm actually very happy with your answer since it probably means that we will not need to re-route our DDR2 memories (depending on our consultants analysis, of course)!

    Ken