I need to know how important it is to have all bits of a DDR2 byte-lane (including data mask and data strobe signals) routed on the same layer of a PWB? And, if this is an important aspect of a DDR2 implementation, why doesn't the "TMS320C6457 DDR Implementation Guidelines" (SPRAAG6D-December 2006- Revised January 2010) explicitly state this as a requirement?
The "TMS320C6457 DDR Implementation Guidelines" also does not make any recommendation for the impedance of the differential lines. It does, however, recommend that all single-ended lines have a nominal characteristic impedance of 50 ohms. Therefore, is it reasonable to conclude that all differential lines need to have a characteristic impedance of 100 ohms?