Am running a Multicore project, which does the following functionality :
Core0 : - Recieves the packet from GIGE port, writes into the buffer in the shared region <MSCMCRAM> .
- Generates CSL_IPC_genGEMInterrupt interrupt to core1 .
Core1: - On reception of interrupt <CSL_IPC_isGEMInterruptSourceSet> reads the data from buffer .
This is my GiGe intialization:
CORE0:
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void MultiCoreApp (Void) { Int32 i; UInt32 coreNum; volatile UInt32 testComplete=FALSE; /* Get the core number. */ coreNum = CSL_chipReadReg(CSL_CHIP_DNUM); System_printf ("************************************************\n"); System_printf ("*** GiGE Intialization Started on Core %d ***\n",coreNum); System_printf ("************************************************\n"); /* Init internal cycle counter */ TSCL = 1; /* Disable L1 and L2 Cache */ //CACHE_wbAllL1d (CACHE_WAIT); //CACHE_setL1DSize(CACHE_L1_0KCACHE); //CACHE_setL1PSize(CACHE_L1_0KCACHE); #ifndef L2_CACHE CACHE_setL2Size(CACHE_0KCACHE); #endif /* Core 0 does the global initialization */ if(!coreNum) { /* Enable PASS power domain */ passPowerUp(); /* Initialize the components required to run the example: * (1) QMSS * (2) CPPI * (3) Ethernet switch subsystem + MDIO + SGMII */ /* Initialize QMSS */ if (Init_Qmss () != 0) { System_printf ("QMSS Global init failed \n"); BIOS_exit (-1); } else { System_printf ("QMSS successfully initialized \n"); } /* Initialize CPPI */ if (Init_Cppi () != 0) { System_printf ("CPPI init failed \n"); BIOS_exit (-1); } else { System_printf ("CPPI successfully initialized \n"); } //int i ; // for(i = 0 ; i <1000 ; i++); /* Init PA LLD */ if (Init_PASS () != 0) { System_printf ("PASS init failed \n"); BIOS_exit (-1); } else { System_printf ("PASS successfully initialized \n"); } /* Initialize the CPSW switch */ if (Init_Cpsw () != 0) { System_printf ("Ethernet subsystem init failed \n"); BIOS_exit (-1); } else { System_printf ("Ethernet subsystem successfully initialized \n"); } /* Setup Tx */ if (Setup_Tx () != 0) { System_printf ("Tx setup failed \n"); BIOS_exit (-1); } else { System_printf ("Tx setup successfully done \n"); } /* Setup Rx */ if (Setup_Rx () != 0) { System_printf ("Rx setup failed \n"); BIOS_exit (-1); } else { System_printf ("Rx setup successfully done \n"); } /* Setup PA */ if (Setup_PASS () != 0) { System_printf ("PASS setup failed \n"); BIOS_exit (-1); } else { System_printf ("PASS setup successfully done \n"); } globalCfgDone=TRUE; } System_printf ("Global Config_Done..Waiting for attached cores...\n"); while(globalCfgDone == TRUE) SYS_CACHE_INV ((void *) &globalCfgDone, 128, CACHE_WAIT); } |
My question is :
# When i run the code without GIGE initialization interrupt flow between cores is happening successfully , but if i run with GIGE interrupt flow between core is disrupted , (i,e) core 0(Master core) is not receiving any interrupt ??
Does GIGE uses any interrupt registers ?
Can anyone help me on this ?
MCSDK version : 2.2.1.03
IPC : ipc_1_25_03_15
CCS : V5.5
Compiler : c6000_7.4.4
