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Changing PLL1 Freq VIA HPI Interface For DM648

larry bernstein
Intellectual 280 points

Hi,

I wanted to know if it possible to change the PLLOUT  ( Core clock)  Frequency via the HPI interface ( we are using HPI boot)   on the DM647.   We have an Clkin1  frequency of 36MHz on the PCB  and want to have the have core clock of 1080MHz   ( 1.1GHz part)..  Thus, we what to have  PLLM  to 0x1D  ( 29) and not the default  value  0x13.


We are following procedure in section 5.2.2.2 of  SPRUEU6B

I read text in section 6.4.2 of the  DM647/8 data shet   " All hosts (i.e., HPI) must hold off accesses to the DSP while the frequency of its internal clocks is
changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed."


Does this mean it is not possible to change core clock if you using HPI boot and the only means to communication is through HPI ?


Thank you for your consideration in this matter.


Larry Bernstein

  • 0
    TI__Guru** 116100 points
    Hi Larry,
    I think, you can change the frequency through PLL registers.

    e2e.ti.com/.../183003
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 280 points

    Titus,

    Thank you for reply and information.  I reviewed the information in the link e2e.ti.com/.../183003 you provided and it indicates we may need to use a secondary boot means to facilitate changing the  PLL output frequency since some registers  require privileged/supervisor (only DSP accesses)   Is that correct ?   This referenced post is in regards to a C6748, would the same apply to a  DM647or DM648.  It also, mentions DDR  initialization registers rather than PLL registers.
     

    Is there a secondary bootloader code example you can provide as requested in the last comment in the post you referenced ?

    How would you interpret the text in section 6.4.2 of the  DM647/8 data sheet   " All hosts (i.e., HPI) must hold off accesses to the DSP while the frequency of its internal clocks is  changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed."


    Thank you

    Larry

  • 0 in reply to larry bernstein
    TI__Guru** 116100 points
    Hi Larry,
    I think, we don't want any supervisor access to access the PLL registers whereas C6748 needs supervisor access like KICK registers.
    Please refer to the chapter 5 in the following link.
    www.ti.com/.../sprueu6b.pdf

    Create a small bootloader that needs to be booted through HPI and that bootloader code must configure the PLL registers.
    Also try to configure the PLL register without bootloader since HPI is able to access the PLL registers.