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TCI6638K2K 10G Ethernet pattern test, help?

srt35
Intellectual 640 points
Other Parts Discussed in Thread: TCI6638K2K

Hi all,

Im working on a custom design board, with keystone II TCI6638K2K SoC. I want to generate a testing pattern for 10G ethernet, so i can check with scope. 

There is no pattern example project related on webpages and no info at user guides.Search some docs about it, Find some realted registers like TEST_EN, TEST_DATA_WORD, PRBS_EN, but description is TBD(ToBeDecided). I try to figure it out what can i generate this pattern. Is there any possible test mode and test pattern?

Im trying 0x34(b00110100) packet to the transfer line, because its b1010101010 with 4b5b encoding.

Any Idea for pattern test? Did you try  anything like this before?

Best Regards,

"KeyStone II Architecture 10 Gigabit Ethernet Subsystem - User Guide" - www.ti.com/.../spruhj5.pdf

  • TI__Guru* 81335 points

    Hi Serhat,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Moved this thread over keystone forum for faster response. 

    We will get back to you on the above query shortly. Thank you for your patience.

  • in reply to Raja
    Intellectual 640 points

    Hi Raja,

    Thank you for your response. Im trying to get some succesful results, but i havent yet.

    I tried to send data 0x34(b00110100)((because its b1010101010 with 4b5b encoding.)) Test failed that 0x34(b00110100) packet to the transfer line, because data send with header and footer bytes together, so its not b1010101...

    I will try to write some PCS-R module PCSR_TX_CTL register, for example tx_test_en, tx_test_dat_sel,tx_test_sel ...


    What do you suggest? Any suggestion would be helpful,

    Best Regards.

  • in reply to srt35
    TI__Expert 5805 points

    Hi Serhat,

    There is PRBS test patterns support through our SERDES. Under MCSDK -> PDK -> CSL -> SRC -> IP -> SERDES_SB there is a "debug" API which allows you to setup these test patterns. http://software-dl.ti.com/sdoemb/sdoemb_public_sw/mcsdk/latest/index_FDS.html

    What exactly are you trying to accomplish? Maybe we could help narrow down the feature you would need. Is it some sort of link characterization work (i.e. bit error testing?). Or an eye scan?

    Kind regards,

    Javier

  • in reply to Javier Malave-Bonet
    TI__Expert 5805 points
    Hi Serhat,
    To be more specific, once you donwload the PDK there should be a document called Serdes_Diag_User_Guide.docx under -> “C:\ti\pdk_keystone2_3_01_xx_yy\packages\ti\diag\serdes_sb” that covers the basics of the pattern based tests for SERDES.
    Regards,Javier
  • in reply to Javier Malave-Bonet
    Intellectual 640 points

    Hi Javier,

    Thank you for your reply.

    I search that directions, i found some serdes configuration source and header files. It seems like serdes configurations for desired setup.I think our problem is not about serdes because we have succesfully transmit and receive data, so our serdes config is OK.

    Let me make it clear; We have 2 custom board, connected with back panel eachother. We configured serdes, send and receive data from 10G ethernet is OK.

    We have a oscilloscope that is capability for measuring 10G signal. So we connect oscilloscope to the back panel exactly 10G ethernet lines. So, we try to see on oscilloscope 10101 pattern. (with 4b5b encoding)

    we tried to send data array with filled 0x34(101010... with 4b5b encoding), but test failed because i think data send with header and footer bytes together, so its not b1010101...

    How should we proceed to see 10101 pattern? is there any config for that pattern?

    Best Regards.

  • in reply to srt35
    TI__Expert 5805 points

    Hi Serhat,


    The 10GBE peripheral is compliant with 10GBase-R (Section 4 802.3) which uses 64b66b encoding.

    When you mentioned that you tried "sending" a data array could you explain the flow of the data:

    1) What direction: K2K out  or K2K in?

    2) Where did the data originate (i.e. Host core, SERDES test pattern)?

    I understand you are not trying to test SERDES itself, but exactly which IP are you trying to characterize/validate? Beyond SERDES characterization to stabilize and validate the electrical physical design (i.e. board layout etc.) what specifically are you trying to achieve with PRBS patterns?


    Regards,

    Javier

  • in reply to Javier Malave-Bonet
    Intellectual 640 points

    Hi Javier,

    Thank you for your reply.

    We have 2 custom design board, connected with back plane.

    1) direction is one K2K out to another K2K in.

    2)We send data throught Serdes(if you ask that)

    We have measure that signal on the back plane with high speed oscilloscope 25 GHz & 80 GSa/s, So we expect to see data on screen.

    With this setup, What are you suggesting for monitoring the data?

    Best Regards.

  • in reply to srt35
    TI__Expert 5805 points

    Hi Serhat,

    Thanks for the reply. I understand your setup much better. But, I guess I am still trying to understand the problem. Is it that you can't establish link? Is the data being corrupted at the receiving K2K? Again, you will not see a 4b/5b pattern as the interface encodes at a 64b66b bit pattern. Otherwise, is the data communication happening as expected?

    Regards,

    Javier