Test MCBSP CPU interrupts in C6657 platform

Dear all , 

I try to test the MCBSP CPU interrupts.  I am using the CpIntc_postSysInt  function to trigger the  functions that are related with the MCBSP.  But the interrupt is not generated and the functions  tx and rx functions are not called. I have gone through the EDMA interrupt setup  and I have used this as template.

Below you can find the piece of the code that I use.

I have defined the following  types 

static xdc_Int const CICO_RX[CPU_CORES][PCM_MAX_LINES] =
{
	/// CIC0_OUT(4+20*n)
    /// CIC0_OUT(5+20*n)
	/// n is the core number
	{
		4,
		5,
	},
	{
		24,
		25
	}
};


static xdc_Int const CICO_TX[CPU_CORES][PCM_MAX_LINES] =
{
	/// CIC0_OUT(6+20*n)
	/// CIC0_OUT(7+20*n)
	{
		6,
		7,
	},
	{
		26,
		27
	}
};

static xdc_Int const  RINT_Event[PCM_MAX_LINES] =
{
	32,
	36
};

static xdc_Int const XINT_Event[PCM_MAX_LINES] =
{
	33,
	37
};


typedef struct mcsbp_fxns_
{
	CpIntc_FuncPtr tx_fxn;
	CpIntc_FuncPtr rx_fxn;
}mcsbp_fxns_t;

static mcsbp_fxns_t const  fxns[] =
{
	{
		&tx_function0,
		&rx_function0,
	},
	{
		&tx_function1,
		&rx_function1
	}

};

In addition to the definition of these types I have written  the following code to set up the  rx and tx events 

cookie 				= Hwi_disable();
	xdc_UInt core_id    = determineProcId();
	//############################################################################
	//NOTE: Reference table 7.33 TMS320C6655/57
	for(line = 0; line < PCM_MAX_LINES; line++)
	{
		/// Trasmit

		CpIntc_mapSysIntToHostInt(core_id, XINT_Event[line], CICO_TX[core_id][line]);
		/// Configures a CpIntc ISR dispatch entry
		CpIntc_dispatchPlug(XINT_Event[line], fxns[line].tx_fxn, line, TRUE);
		///Enables the host interrupt
		CpIntc_enableHostInt(core_id,  CICO_TX[core_id][line]);
		// Enable the System Interrupt
		CpIntc_enableSysInt(core_id, XINT_Event[line]);
		int tx_event = CpIntc_getEventId(CICO_TX[core_id][line]);
		EventCombiner_dispatchPlug (tx_event, CpIntc_dispatch, CICO_TX[core_id][line], TRUE);
		EventCombiner_enableEvent(tx_event);

		//############################################################################
		// receive
		CpIntc_mapSysIntToHostInt(core_id, RINT_Event[line], CICO_RX[core_id][line]);
		/// Configures a CpIntc ISR dispatch entry
		CpIntc_dispatchPlug(RINT_Event[line], fxns[line].rx_fxn, line, TRUE);
		/// Enables the host interrupt
		CpIntc_enableHostInt(core_id,  CICO_RX[core_id][line]);
		/// Enable the System Interrupt
		CpIntc_enableSysInt(core_id, RINT_Event[line]);
		int rx_event = CpIntc_getEventId(CICO_RX[core_id][line]);
		EventCombiner_dispatchPlug (rx_event, CpIntc_dispatch, CICO_RX[core_id][line], TRUE);
		EventCombiner_enableEvent(rx_event);
	}
	Hwi_enableInterrupt(7);
	/* Restore interrupts */
	Hwi_restore(cookie);

I cannot find where is the problem and the related functions are not called.

But when I map the groups with the interrupts in the cfg file , all works fine. But  i do not want this approach. I would like to set up  the interrupts using C code

/*example in cfg */
ECM.eventGroupHwiNum[0] = 7;
ECM.eventGroupHwiNum[1] = 8;
ECM.eventGroupHwiNum[2] = 9;
ECM.eventGroupHwiNum[3] = 10;

Could you please help me with this issue?

Best regards

George