About BBB ddr size change to 256MB(2Gbit) from 512MB(4Gbit)

Hi Joe,

For calculating EMIF register values please use the following wiki: processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips & DDR calculation tools pointed in it.

As for the DDR size displayed by u-boot see:
include/configs/ti_am335x_common.h - #define CONFIG_MAX_RAM_BANK_SIZE
The memsize calculation & meminit is done in common/board_f.c , common/memsize.c & board/ti/am335x/board.c

Also can you please clarify which u-boot version are you using?

Best Regards,
Yordan

Hi Yordan,

It still is 512M after modify the CONFIG_MAX_RAM_BANK_SIZE of ti_am335x_common.h to (512 << 20) from (1024 << 20)

and modify MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2//0x61C05332.

below is my uboot(SDK8.0) message
U-Boot 2014.07-00107-gd28f2b9-dirty (Apr 08 2015 - 14:38:58)

I2C: ready
DRAM: 512 MiB
NAND: 0 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
reading uboot.env

** Unable to read "uboot.env" from mmc0:1 **
Using default environment

Net: <ethaddr> not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 0
U-Boot#
U-Boot# md 0x4C000008
4c000008: 61c052b2 00000000 00000c30 00000c30 .R.a....0...0...

B.R.
Joe

Joe,

I think you need to modify CONFIG_MAX_RAM_BANK_SIZE to (256 <<20)

However I am not sure, why your u-boot cannot calculate the DDR size correctly.  I use the prebuilt u-boot (SDK8.0) on Beablebone Black and the message is DRAM: 512 MiB. But when I use the same u-boot (from SDK8.0) to boot Beaglebone White (RAM = 256 MiB), the boot message is changing to DRAM: 256 MiB. I do not modify anything in u-boot sources during my test.

Best Regards,
Yordan

Hi Yordan,

Thanks. It is workable after changing CONFIG_MAX_RAM_BANK_SIZE to (256 <<20), but I think the uboot should modify MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2//0x61C05332. Due to ddr size is row*column*banks*data bus, our ddr row size is 0~14, the BBB's row size is 0~15, right?

B.R.
Joe

Hi Joe,

I guess this MT41K256M16HA125E_EMIF_SDCFG is a register of the memory device (MT41K256M16HA125E), right? Looking at the TRM, I can't find it in AM335x EMIF registers...

Best Regards,
Yordan

Hi Yordan,

The control_emif_sdram_config could be find the AM335x_TRM page 1373

9-7 ROWSIZE Defines the number of row address bits of connected SDRAM devices.

Due to ddr size is row*column*banks*data bus, our ddr row size is 0~14, the BBB's row size is 0~15

To set control_emif_sdram_config = MT41K256M16HA125E_EMIF_SDCFG = 0x61C052B2; right?

B.R.
Joe

Sorry, I got confused because you were referencing MT41K256M16HA125E_EMIF_SDCFG . Anyway for EMIF Configuration tips check: processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips

Use your DDR datasheet & DDR Calculation tool (processors.wiki.ti.com/.../AM335x_DDR_register_calc_tool.zip) in order to set the correct EMIF timing & config values.

Best Regards,
Yordan