C641x UTOPIA queue max size

Jeff,

The Queue size is not defined, but not required either.  The Element Size of the transfer should never exceed the ATM Cell Size (56B max.)  And when there's 56B or more available in the Queue the UXEVT will be generated telling the EDMA to send the next Element Size worth of data.  So it's transparent to the user if the directions for setting up the EDMA transfers as described in SPRA952 are used.

Best Regards,

Chad

Chad-

> The Queue size is not defined, but not required either.

Thanks for your answer, but I disagree.  Several years of C64x programming experience teaches there are many things that can stall DMA -- other EDMA, HPI access, even CPU pipelining situations where the core monopolizes internal memory bus usage.

I found that pg 3 in SPRA952 says:

    Both the transmit and receive queues accommodate a total of two cells.

So this would mean that we need to prevent EDMA stalls lasting longer than about 2 usec (transfer time for 2 cells at 50 MHz).

Can you confirm the two-cell size for UXQ and RXQ?  If not please point me to a TI engineer who can, thanks.

-Jeff

Jeff,

I may be incorrect here, but my understanding is that an internal stall of data, unless it exceeds the host requirements, would not be an issue and handshaking is provided for this.

Do to this, I assumed you were concerned about possible over fill the queue on the transmit side, which wouldn't be possible w/ correct EDMA setup.  Also, the overfilling of the queue on the receive side would not be possible do to the URCLAV pin (i.e. if the queue doesn't have room it won't allow the host to transmit.)

Best Regards,

Chad

Chad-

> I may be incorrect here, but my understanding is that an internal stall of
> data, unless it exceeds the host requirements, would not be an issue
> and handshaking is provided for this.

No we are concerned about receive because we must maintain the full 50 MHz rate, or close to it.  In our application modulating the URCLAV pin wouldn't help since our remote end is GbE, which of course has nearly 2x the max C64x UTOPIA rate (UTOPIA-to-GMII conversion is taking place inside an FPGA).

This is why we're very concerned about what constraints we face on EDMA stalls, and thus the queue size question.

Again can you just please confirm the 2-cell size, or give us the actual size.  Thanks.

-Jeff

Jeff,

I got confirmation from one of the engineers who worked on the development of the device that it's two ATM cells deep.

Best Regards,

Chad