Fast GPIO output with TIRTOS

This is just a follow-up of the thread at https://e2e.ti.com/support/embedded/tirtos/f/355/p/408900/1463878#1463878.

Somebody has marked a post as “suggested answer” and that seems to be the reason why there is no “Reply” button any longer and I have to open this new thread.

Hi Ashish and Pratheesh,

sorry for my late reply. Thank you very much for your comments.

I am now using GPIO0 instead of GPIO3 because that was the port where  the code was running with Starterware and BBB beford, but the result is still the same. Still 215ns.

This is the minimized code snippet I am using for the test:

void main()
{	MAC_CONFIG config;
        int i; 
	MMUInit(applMmuEntries); // function from osdrv_mmu.c
	Cache_enable(Cache_enableCache); // Enable L1 and L2 data and program caches


#ifdef TEST_GPIO0_19
	UInt way1, way2;

	// the array Table40ns[] contains 20 integer values that are read be SenderAnsteuerung()
	way1 = Cache_lock((Ptr *) Table40ns, 20*8); // returns 0x80

	// The function SenderAnsteuerung() reads values from Table40ns[] and writes to GPIO0
	way2 = Cache_lock((Ptr *) SenderAnsteuerung, 20*8); // returns 0x40

   	ICSS_SWITCH_CONFIG switchConfig={QUEPRIO4,1,0}; //default params
	PinMuxConfig(iceMux);
	PinMuxConfig(icev2Mux); // gesetzt in appl_cnfg.h
	PinMuxConfig(muxConfig_in);  // GPIO3_20, zusätzlich als Test-Output

    	InitGpio0(); // I am using GPIO0 instead of GPIO3 to see if it makes any difference, but it doesnt
    	while(1) {
    		SenderAnsteuerung((unsigned int) Table40ns, SOC_GPIO_0_REGS + GPIO_DATAOUT); // writes to GPIO
    	}
#endif  // TEST_GPIO0_19

	.
	.
	.
}

Is that cache loading and locking correct? It looks to me as if  there is no conflict with Starterware code. The only function that contains code from Starterware is InitGPIO0(), but no cache or mmu code.

 In app.cfg I set the peripheral section to bufferable and cacheable:

/* MAP CM_PER Register Space in MMU */
/* Force peripheral section to be NON cacheable */
var peripheralAttrs = {
    type : Mmu.FirstLevelDesc_SECTION, /* SECTION descriptor */
    bufferable : true,		        // original: false,
    cacheable  : true,		// original: false,
    shareable  : false,
    noexecute  : true,
};

/* Define the base address in which the peripherals reside. */
/* Clock Module, GPIO0, UART0, I2C0 */
var peripheral0BaseAddr = 0x44E00000

/* Configure the corresponding MMU page descriptor */
Mmu.setFirstLevelDescMeta(peripheral0BaseAddr, peripheral0BaseAddr, peripheralAttrs);

That did not improve the situation.

Next comes MMUInit(). That applMmuEntries[] table is still causing some headache to me:

There is an entry

         {(void*)0x44E00000,0},  // Non bufferable| Non Cacheable

To make the GPIO0 registers bufferable and cacheable I added this line:

         {(void*)0x44E07000,SYS_MMU_CACHEABLE + SYS_MMU_BUFFERABLE},

and alternatively also replaced both lines by

        {(void*)0x44E00000,SYS_MMU_CACHEABLE + SYS_MMU_BUFFERABLE},

But the result was that the GPIO0 pin is no longer toggled.

Stopping the debugger led to the message

       Can't find a source file at     "D:/x0159762/Projects/IndSDK/Source/Ref_repo/GIT_NO_DEV/public/sdk/starterware/platform/evmAM335x/hsi2c.c"

       Locate the file or edit the source lookup path to include its location.

 So for some reason SYS_MMU_CACHEABLE + SYS_MMU_BUFFERABLE are not accepted.

Can you suggest what to do? I am attaching app.cfg. Perhaps there is something wrong with the file.

 Regards,

Martin H.0160.app.cfg