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PCIe Outbound Write Address Translation

Ilan Bogen
Intellectual 330 points

aHi,

I have a question about the address translation of the following request:

Transmitting an 8MB buffer located at 0x80000000-0x80800000 to to a PC with PCIe address = 0x8CB22000.

As I understand from the example PCIe Outbound Address Translation in PCIe UseCases for Keystone Devices:

CMD_STATUS[OB_XLT_EN] = 1

OB_SIZE = 8MB

Transfer to PCI_Data:  dataSize = 8MB, srcAddr = 0x80000000, dstAddr = 0x60000000

OB_OFFSET_INDEX0 = 0x8CB22001 ( PCIe address with enabling the region)

OB_OFFSET0_Hi = 0x0

According to the example the translated address will be:

bits[31:23] of 0x8CB22000 + bits[22:0] of 0x60000000 = 0x8C800000 (bits 22:0 are zeroed)

To get the correct PCIe address I need to split the PCI address between the 2 elements as follows:

Transfer to PCI_Data:  dataSize = 8MB, srcAddr = 0x80000000, dstAddr = 0x60522000

OB_OFFSET_INDEX0 = 0x8CB22001 (Outbound PCIe address with enabling region 0)

OB_OFFSET0_Hi = 0x0

OB_OFFSET_INDEX1 = 0x8CE00001 (Remaining of buffer and enabling region 1)

OB_OFFSET1_Hi = 0x0

bits[31:23] of 0x8CB22000 + bits[22:0] of 0x60522000  = 0x8CB22000

This will cause the 8MB buffer to be transfered via 2 regions; region0 and region1.

It seems wrong to me.

What is the right way to do it?

Thanks,

Alan.

  • 0
    TI__Mastermind 28085 points
    Hi,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    PCIe address translation is clearly document in PCIe programmer user guide with example, refer section "3 PCIe Address Translation" and "3.1.1 PCIe Outbound Address Translation Examples" on PCIe Use Cases document for KeyStone Devices(SPRABK8).

    www.ti.com.cn/.../sprabk8.pdf

    Please go through below wiki for PCIe related FAQs and Resources.

    processors.wiki.ti.com/.../PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 330 points
    Hi Ganapathi,

    Thank you for the prompt answer.
    As I wrote in my post, I already read the sprabk8.pdf.

    In the example the PCIe address is 0x70000000 that doesn't have a problem with taking out only its 9 MSB.
    ( BTW, I have a problem understanding how can it be chosen randomly, and if it is so why choosing it at all,
    set it as a constant)
    The question is what about a PCIe address that is given (0x8CB22000) and can't be chosen,
    what about bits 22:0, how are they going to be treated?

    Thanks,
    Alan.
  • 0 in reply to Ilan Bogen
    TI__Mastermind 28085 points

    Hi,

    If OB_SIZE = 8 MB means you need to choose following region for the transaction(0-31).
    Bits[27:23] of internal address are used for region identification
    Bits[31:23] of OB_OFFSET_INDEXn are used for translation
    In KeyStone devices, the region allocation is as follows:
    0x6000_0000~0x607F_FFFF is for Region 0 (bits[27:23]=0)
    0x6080_0000~0x60FF_FFFF is for Region 1 (bits[27:23]=1)
    ......
    0x6F00_0000~0x6F7F_FFFF is for Region 30 (bits[27:23]=0x1E=30)
    0x6F80_0000~0x6FFF_FFFF is for Region 31 (bits[27:23]=0x1F=31)

    If you want to use dstAddr = 0x60522000 means you need to reduce the OB size for pcie transfer.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 330 points

    Hi,

    Thanks again.

    I think that my question is not clear enough so I'll try to rephrase it.

    I want to transmit an 8MB buffer located at 0x80000000-0x80800000 to an internal buffer in a PC with a given PCIe address = 0x8CB22000.

    As I understand from the example in the PCIe UC:

    CMD_STATUS[OB_XLT_EN] = 1

    OB_SIZE = 8MB

    I would like  to use region 0, so I transmit the data  to PCI_DATA address 0x60000000  (bits [23:27] = 0) 

    Transfer to PCI_Data:  dataSize = 8MB, srcAddr = 0x80000000, dstAddr = 0x60000000

    OB_OFFSET_INDEX0 = 0x8CB22001 ( PCIe address with enabling the region)

    OB_OFFSET0_Hi = 0x0

    Are the above settings correct ? If not, what should be the right setting?

    According to the example the translated address will be:

    bits[31:23] of 0x8CB22000 + bits[22:0] of 0x60000000 = 0x8C800000 (bits 22:0 are zeroed).

    Am I right? If not, what is the translated address?

    I understand that the translated address should be equal to the destination given PCI address 0x8CB22000, am I right?

    Thanks again,

    Ilan.

  • 0 in reply to Ilan Bogen
    TI__Mastermind 28085 points

    Hi,

    As per PCIe user guide OB_OFFSET_INDEX register OB_OFFSETn_LO write access bit filed(31-20) and OB_ENABLEn bit field(0), other bit fields are reserved. User can able to choose the PCIe address based on the OB_OFFSETn_LO bit filed(31-20). If you write 0x8CB22000 address means the reserved bit field are not updated on OB_OFFSETn_LO register.

    Thanks,