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McASP frame sync and clock divider

Szymon Kuklinski
Intellectual 835 points
Other Parts Discussed in Thread: OMAP-L138

Hello

I have two questions regarding how McASP treats the frame sync signal and how it divides the incoming clock.

1) Can a longer FS signal be used? My OMAP-L138 device is clocked and synced form a device that cannot provide a FS lasting 1 bit or 1 word. The only option is a 50/50 signal. As far as I know McBSP was far more flexible in this matter.

2) Is dividing the clock signal somehow synchronized to the frame sync? I'm getting two outputs of a divided signal in random order: one is the correct one in which my clock signal has a rising edge on the beginning of FS, and the other in which the clock has a falling edge on that moment. The two waves have the correct frequency, but as you can see I can't rely on that type of division. The interesting thing is that once McASP starts working it either divides the clock one way or another, as if the divider was only synchronized on the first FS and a race condition either went my way or not. Can it be caused by the fact that I have to reshape the FS signal to comply to the requirements given in the documentation? It imposes about 8ns delay.

Regards
Szymon

  • 0
    TI__Guru 62975 points

    Szymon,

    Yes, the McBSP is more flexible with frame sync pulse width.  Can you explain how the 50/50 signal works?  Do you mean that the signal can only remain high for half of the word?

    The framesync does need to be internally synchronized with the reference clock so it's possible that there is a race condition.  There are datasheet setup and hold times between frame sync and reference clock that need to be maintained so 8ns could be violating those relationships.

    -Tommy