Frame size vip0a

mike A

Hi,

referring to post [1] which says the offset of vip0 port A, when I try and dump this value it doesnt match to my expected size (1920X1080) (0x07800438), (my value is 0x00940001). So my question is how does the firmware set this register ? Since I am trying to capture from the frames from fpga I have removed the control component from capture_encode example. I tried setting this register manually with devmem but doesn’t help either can someone please throw some light on this.

[1]

Thanks And Regards,

Mike

over 10 years ago

0 Brijesh Jadav over 10 years ago

TI__Guru**** 477995 points

There is no firmware to configur this. This is in the hardware, it counts number of hsync/vsync signals inputs and provides the values of them in this read only register. If you are not getting correct value, VIP is not receiving data correctly.

Regards.

Brijesh

0 mike A over 10 years ago in reply to Brijesh Jadav

Genius 3490 points

Hi Brijesh,

Thanks for the response!

in my case I am trying to capture it from the FPGA with embedded syncs & not discrete sysnc's how can I make sure its correct ?

Thanks And Regards,
Mike

0 Brijesh Jadav over 10 years ago in reply to mike A

TI__Guru**** 477995 points

In this case, your sync codes are not correct. please check in the fpga logic.
Also please try inverting pclk polarity.Rgds,Brijesh

0 mike A over 10 years ago in reply to Brijesh Jadav

Genius 3490 points

Hi Brijesh,

I couldn’t get what you meant from ' inverting pclk polarity' from the davicni side or the fpga side ?
if from davinci side is there any openmax api to do it ?

Thanks And Regards,
Mike

0 mike A over 10 years ago in reply to Brijesh Jadav

Genius 3490 points

Hi Brijesh,

The OMX_PARAM_VFCC_HWPORT_PROPERTIES structure doesnt have any polarity configuration parameter into it!
Any pointer on how to do it ?

Thanks And Regards,
Mike

0 mike A over 10 years ago in reply to Brijesh Jadav

Genius 3490 points

Hi Brijesh,

By default on the release on dm8148 the data is sampled on -ve edge ?
In our case from fpga side the pixel data changes on +ve edge of pixel clock.

Thanks And Regards,
Mike

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Frame size vip0a