Hey,
I use the EtherCAT example with on the Sitara IDKv2 and a DCAN0 driver.
The EtherCAT example uses the Cache, which generates a problem with the DCAN0 message buffers.
Cache_lock ((Ptr)0x40300000,0x8000); Cache_wait(); Cache_lock ((Ptr)0x40308000,0x8000); Cache_wait(); Cache_lock ((Ptr)0x80000000,0x8000); Cache_wait(); Cache_lock ((Ptr)0x80008000,0x8000); Cache_wait(); Cache_lock ((Ptr)0x80010000,0x8000); Cache_wait(); Cache_lock ((Ptr)0x80018000,0x8000); Cache_wait();
As the DCAN0 registers are at adress
0x481C_C000 to 0x481C_DFFF (DCAN0 0x481C_C000 0x481C_DFFF 8KB DCAN0 Registers, spruh73i.pdf manual page 174)
i don't see a problem where the cache could interfere in this case.
However the exact problem is not to access the registers described at the above adresses. It is more a problem of accessing the message buffers.
So if I write to a specific message buffer via one of the interface registers (IF1 or IF2) the data is not correctly written to the message buffer. I can verify this by reading the message buffer (via IF1) directly after it is written (via IF2)
How can the cache interfere with the message buffers of the CAN controller? (are they in a special adress range of the controller?)
I also tried to comment the cache lines, this makes the project work. But the EtherCAT example does not work as expected. The node is not configured correctly, all data which can be read online by use of TwinCAT is 0 (e.g. vendor ID = 0)
So I suppose the EtherCAT data is not correctly initialized if the cache was not configured.
Please help either:
- How can I get the EtherCAT to work without the cache?
or
- How can I get the CAN driver to work correctly with the cache?
