I am attempting to setup PCIe INTA on a C6678(PCIe Root complex) to a PLX 3380 USB device(PCIe endpoint)
I am setting up the interrupt as follows:
//Map secondary inputs to the Core event
CpIntc_mapSysIntToHostInt(0, 50, 32); // I picked host int 32 for CPINTC #0. CPINTC #1 is for cores 4-7
CpIntc_dispatchPlug(50, &INTA_Event_isr, 50, TRUE); //
CpIntc_enableHostInt(0, 32); // CPINT #0 is for cores 0-3, CPINTC #1 is for cores 4-7
eventId = CpIntc_getEventId(32); // this should return the GEM event 21 (This was a bug fixed in 6.32.04)
Hwi_Params_init(&hwi0Params);
hwi0Params.arg = 32; // required to be the host interrupt #
hwi0Params.eventId = eventId;
hwi0Params.enableInt = TRUE;
hwi0Params.priority = 4;
Hwi_create(6, &hwi_isr, &hwi0Params, NULL); // create ISR to handle this event in Hwi vector 6
Hwi_enableInterrupt(6);
Hwi_enable();
I can manually trigger an event/HWI pair by using this:
((CSL_CPINTC_RegsOvly)CSL_CP_INTC_0_REGS)->STATUS_SET_INDEX_REG = 50;
and everything gets handled correctly, so I have some confidence that my event and HWI are mapped correctly. However if I setup the INTA by setting
LEGACY_A_IRQ_ENABLE_SET and then writing to the LEGACY_A_IRQ_STATUS_RAW, I do not get an event to occur.
What am I missing? Since this is not occurring, I am uncertain if my endpoint is function correctly or not.
I am assuming that Enable_SET is at 0x2180_0188 and _RAW is at 0x2180_0180. When I breakpoint, I can see that these are both set to 0x01, but I do not hit a breakpoint in the event handler as I will when using the CPINTC function above.
using the GEL file from the forum to view interrupts, the below shows that the PCIe Legacy Interrupt A (0) is mapped to host32, as shown above in the code sample, and that the interrupt is enabled, and an interrupt is pending to be serviced. So why does it not trigger the event and ISR on Core 0?
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: ********************************** PCIE CHANNEL MAP *******************************************
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: Protocol Error Interrupt (PCIEXpress_ERR_INT) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: Power Management Interrupt (PCIEXpress_PM_INT) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: Legacy Interrupt Mode 0 (PCIEXpress_Legacy_INT0) ---> INTC0_OUT32
C66xx_0: GEL Output: Legacy Interrupt Mode 1 (PCIEXpress_Legacy_INT1) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: Legacy Interrupt Mode 2 (PCIEXpress_Legacy_INT2) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: Legacy Interrupt Mode 3 (PCIEXpress_Legacy_INT3) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: ********************************** PCIE EVENTS ENABLE/DISABLE *******************************************
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: Protocol Error Interrupt (PCIEXpress_ERR_INT) is **DISABLED**
C66xx_0: GEL Output: Power Management Interrupt (PCIEXpress_PM_INT) is **DISABLED**
C66xx_0: GEL Output: Legacy Interrupt Mode 0 (PCIEXpress_Legacy_INT0) is ##ENABLED##
C66xx_0: GEL Output: Legacy Interrupt Mode 1 (PCIEXpress_Legacy_INT1) is **DISABLED**
C66xx_0: GEL Output: Legacy Interrupt Mode 2 (PCIEXpress_Legacy_INT2) is **DISABLED**
C66xx_0: GEL Output: Legacy Interrupt Mode 3 (PCIEXpress_Legacy_INT3) is **DISABLED**
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: ********************************** PCIE EVENTS RAW STATUS *******************************************
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: Protocol Error Interrupt (PCIEXpress_ERR_INT) is ##NOT PENDING##
C66xx_0: GEL Output: Power Management Interrupt (PCIEXpress_PM_INT) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 0 (PCIEXpress_Legacy_INT0) is **PENDING**
C66xx_0: GEL Output: Legacy Interrupt Mode 1 (PCIEXpress_Legacy_INT1) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 2 (PCIEXpress_Legacy_INT2) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 3 (PCIEXpress_Legacy_INT3) is ##NOT PENDING##
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: ********************************** PCIE EVENTS ENABLED STATUS *******************************************
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: Protocol Error Interrupt (PCIEXpress_ERR_INT) is ##NOT PENDING##
C66xx_0: GEL Output: Power Management Interrupt (PCIEXpress_PM_INT) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 0 (PCIEXpress_Legacy_INT0) is **PENDING**
C66xx_0: GEL Output: Legacy Interrupt Mode 1 (PCIEXpress_Legacy_INT1) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 2 (PCIEXpress_Legacy_INT2) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 3 (PCIEXpress_Legacy_INT3) is ##NOT PENDING##
