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Problems when trying to change the C6747s clock rate

Markus Grunwald
Expert 2060 points

Hello,

to save some power, we tried to change the clock rate of the DM814x's C6747. Two problems arise:

1) When doing it from Linux, using devmem, that's what happens:

/ # devmem 0x481c5090 32
0x00020013
/ # devmem 0x481c5090 32 10013
/ # devmem 0x481c5090 32
0x00020013

So the register content doesn't change :(
(by the way: doesn't the '2' in the read value mean that the DSP is running at half the clock rate?)

2) When we stop booting in UBOOT and change the register there, the register change seems to work. But then, this happens when loading our DSP:

ERROR HOOK !!!!
 * Unknown: 372178944 (0x162f0000)
 * E_freqMismatch: Frequency mismatch: Expected 20000000 Hz, actual: 45675020 Hz.  You need to modify Timer.intFreq.lo to match the actual frequency.
 * Code=11897
 * ModuleID=32810 (0x802a)
 * Line=1111
 * File="i"

So it seems that I can use a DSP firmware only for one clock rate? Can't I change the clock rate on the fly?

Thanks for your help,

Markus

  • 0
    TI__Guru**** 170625 points

    Hi Markus,

    Markus Grunwald said:
    to save some power, we tried to change the clock rate of the DM814x's C6747

    In EZSDK 5.05.02.00 DM814x C674x DSP frequency is set to 500MHz by default. At what lower frequency you need to set the DSP? Or you need to set the DSP PLL to idle bypass mode when not needing the DSP core?

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_04.04.00.02_Feature_Performance_Guide#Clock_Rates 

    Markus Grunwald said:

    1) When doing it from Linux, using devmem, that's what happens:

    / # devmem 0x481c5090 32
0x00020013
/ # devmem 0x481c5090 32 10013
/ # devmem 0x481c5090 32
0x00020013

    I am using devmem2 tool (not devmem) and I have the value you are trying to set by default:

    root@dm814x-evm:~# devmem2 0x481C5090
    /dev/mem opened.
    Memory mapped at address 0x40286000.
    Read at address  0x481C5090 (0x40286090): 0x00010013

    root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/dsp_dpll_ck/gem_fck# cat rate
    500000000

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Expert 2060 points

    Pavel Botev said:
    In EZSDK 5.05.02.00 DM814x C674x DSP frequency is set to 500MHz by default. At what lower frequency you need to set the DSP? Or you need to set the DSP PLL to idle bypass mode when not needing the DSP core?

    We'd like to save power while the DSP core is not really needed. Out first approach was to twiddle with the mentioned registers to set a lower external clock rate (the default is at 20MHz IIRC?).

    That failed because of two reasons:

    1.  we couldn't change the register using devmem or devmem2 when linux is running.
    2. when we changed the register in UBOOT, we got the strange error message. Strange because we haven't expected the "actual: 45675020 Hz", so it seems there's something wrong, too.

    Can you explain any of the two points?

    Our other approaches are to change the idle loop and maybe to use the SYSBIOS Power Module. Regarding the last one: is the power module still not supported on the C6747 but only on the C6748? Can we use it anyway, somehow?

    Thanks for your help!

    Markus

  • 0 in reply to Markus Grunwald
    TI__Guru**** 170625 points

    Markus,

    Markus Grunwald said:
    •  we couldn't change the register using devmem or devmem2 when linux is running.

    I think you can modify this register only in supervisor/privileged mode, thus not possible from user space (user mode) with devmem2 tool. You should be able to modify this register from linux kernel and/or u-boot where you are in supervisor/privileged mode.

    Markus Grunwald said:
    when we changed the register in UBOOT, we got the strange error message. Strange because we haven't expected the "actual: 45675020 Hz", so it seems there's something wrong, too.

    I have the value of 0x00010013 in DSPPLL_M2NDIV register by default in u-boot also, then I do not have strange error message. So you need to focus why you have 0x00020013 value there.

    BR
    Pavel