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[C5535] Power consumtion

Kaka
Guru 24520 points

Hi community member, 

please let me confirm the following question.

[Question]

 Is there a difference in power consumption in the following case? 

 1. Always supply the voltage for USB power domain even though the device enter the low power mode.

     Note: When the device enter the low power mode, the USB module will be disabled by register.

 2.  USB power domain will be removed when the device enter the low power mode.

If you have any question, please let me know.

Best regards.

Kaka

  • 0
    TI__Genius 12575 points

    Hi kaka-san,

    Below are my response for your cases.

    1.   Yes, by stopping USB clocks, it is possible to reduce the USB's active power consumption (in the digital logic) to zero. Stopping clocks to a peripheral only affects active power consumption; it does not affect leakage power consumption. USB leakage power consumption can be reduced to zero by not powering the USB.

     2.  Yes I believe you can in order to reduce the leakage current. But the below data needs to be considered for this (This is mentioned in silicon Errata SPRZ373).

    The USB oscillator is disabled by writing a '1' to the USBOSCDIS bit of the USBSCR register. Whenever voltage to the core is removed (for example, during RTC-only mode), the value written to the USBOSCDIS register is lost. If the USB I/O supplies are supplied, the USB oscillator reactivates and consumes power. To disable the USB oscillator when core voltage is removed, the user must power down all USB I/O supplies (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL).

    Hope the above helps.

     Regards

      Vasanth

  • 0 in reply to Vasantha K
    Guru 24520 points

    Hi Vasanth,

    Thank you for your response.
    Please let me confirm my understanding.
    In No.1 case, if disabled the USB PLL, it is possible to reduce the USB active power consumption. However there is the USB leakage power consumption if not reduce the power line.
    The USBPWDN bit on USBSCR register will be set by software, we could reduce the power consumption.

    Is my understanding correct?

    And would you please provide the data of the USB leakage power in case of not removing the USB power such as USB_VDPLL,USB_VDDA3P3?


    Best regards.
    Kaka

  • 0 in reply to Kaka
    TI__Genius 12575 points

    Hi Kaka-san,

      As mentioned in C5535 Technical Reference Manual - Asserting USBPWDN puts the USB PHY and PLL in their lowest power state.

      With respect to USB leakage power, you could download the power spreadsheet from the below wiki link download section and follow the procedure mentioned below.

      http://processors.wiki.ti.com/index.php/TMS320C5504/05/14/15/32/33/34/35_Power_Consumption_Summary

      Select/click on "Idle3" macro and set usb module in "idle" mode. Data on USB3v3 and USB1v3 will provide the typical USB leakage current .

      Similarly, you could find typical leakage data with respect to other power domains too.

      Hope this helps.

    Regards

     Vasanth

     

  • 0 in reply to Vasantha K
    Guru 24520 points
    Hi Vasanth,
    Thank you for your response.
    I will inform this information to my customer.
    Best regards.
    Kaka