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[C6748] DDR2/mDDR Memory Controller Clock Stop Procedure

Thomas Price7137
Intellectual 625 points
Other Parts Discussed in Thread: OMAP-L138

Hi-

I'm currently running code on a C6748 chip and am doing experiments in putting the chip into Deep Sleep. I'm also doing power measurements to see how much power is being drawn from the SOM when I'm in this power state. I'm still seeing a significant amount of power being drawn by the SOM even in deep sleep mode, so I wanted to test shutting down the DDR memory while being in sleep mode to see if it has much of an effect. I've been reading sprugj4.pdf which is the "DDR2/mDDR Memory Controller" User Guide and it has a section that describes how to do this. The section talks at a bit too abstract of a level for me to track down all the correct registers and bit definitions. Does anyone have a "For Dummies" code example that does what the user guide describes? (I've pasted it below)

 

 

 

To achieve maximum power savings VCLK, MCLK, 2X_CLK, DDR_CLK, and DDR_CLK should be gated

off. The procedure for clock gating is described in the following steps.

1. Allow software to complete the desired DDR transfers.

2. Change the SR_PD bit to 0 and set the LPMODEN bit in the DDR2 SDRAM refresh control register

(SDRCR) to enable self-refresh mode. The DDR2/mDDR memory controller will complete any

outstanding accesses and backlogged refresh cycles and then place the external DDR2/mDDR

memory in self-refresh mode.

3. Set the MCLKSTOPEN bit in SDRCR. This enables the DDR2/mDDR memory controller to shut off the

MCLK.

4. Poll the PHYRDY bit in the SDRAM status register (SDRSTAT) to be a logic-low indicating that the

MCLK has been stopped.

5. Program the PSC to disable the DDR2/mDDR memory controller VCLK. You must not disable VCLK in

power-down mode; use only for self-refresh mode (see notes in this section).

6. Program PLLC1 registers to stop 2X_CLK to DDR2/mDDR memory controller, as well as DDR_CLK

and DDR_CLK. You must note disable 2X_CLK in power-down mode; use only for self-refresh mode

(see notes in this section). For information on programming PLLC1, see your device-specific

 

 

System Reference Guide

 

 

  • 0
    TI__Guru 62975 points

    Thomas,

    I'll ask around for code snippets.  Did this other code sample worK?

    http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/p/41059/143693.aspx#143693

    -Tommy

  • 0
    Prodigy 220 points

    Hi Thomas and Tommy,

    Was a solution ever discovered for this problem? I am trying to put DDR in self refresh mode and am having trouble with steps 5 and 6 that are listed above. Conversely, I'll also need to know how to turn the clocks back on, but I assume that will be fairly obvious once I know how to turn them off. The steps to turn on the clocks as listed in the DDR2/mDDR Memory Controller User's Guide are:

    1. Place the PLL/PLLC1 in PLL mode to start 2X_CLK to the DDR2/mDDR memory controller.
    2. Once the 2X_CLK is stable, program the PSC to enable VCLK.
    3. Set the RESET_PHY bit in the DDR PHY reset control register (DRPYRCR) to 1. This resets the DDR2/mDDR memory controller PHY. This bit will self-clear to 0 when reset is complete.
    4. Clear the MCLKSTOPEN bit in SDRCR to 0.
    5. Clear the LPMODEN bit in the DDR2 SDRAM refresh control register (SDRCR) to 0.

    I can do steps 3-5, but I'm having trouble with steps 1 and 2.

    Thanks,
    Wes

  • 0 in reply to Wesley Denlinger
    TI__Mastermind 27585 points

    For putting the DDR in self refresh, see the System Reference Guide figure 7-3:

    5) PSC1-6 controls the DDR2/mDDR VCLK, so change the state to Disable.

    6) To turn off the 2X_CLK, disable the PLLDIV1 which sources it.

    For reenabling it, steps 1 and 2 are the same as above just doing the reverse operation.

    Jeff

  • 0 in reply to jc-ti
    Prodigy 220 points

    Hi Jeff,

    Thank you for your reply. I had seen that figure but hadn't made the connection that LPSC #6 is PSC1-6 or where to disable PLL1_SYSCLK1. I've made the necessary changes and the omap-l138 appears to be going into self-refresh mode. I'm trying to develop a test that will test the DDR. The idea was that I would write to all the addresses, put the DDR in self-refresh mode, wait for a period that is 1000 times the length of the refresh period, take the DDR out of self-refresh mode, then read all of the data back to verify that it is still correct. That seems to work, i.e. all of the data is what was written to it.

    However, as a control, I performed the same steps, but instead of putting the DDR in self-refresh mode, I'm putting it in power-down mode (SR_PD is set to 1 and I'm not disabling VCLK or 2X_CLK, as documented). Again, I wait 1000 times the refresh period (64 seconds) and then read the data back. The problem I'm having is that the data is all correct. I'm running in Emulation mode on the omapl-138.

    Any suggestions as to why the data is still being refreshed?

    Thanks,
    Wes

  • 0 in reply to Wesley Denlinger
    TI__Mastermind 27585 points

    We would need some more details to determine why if it still refreshing when the SR_PD is set.

    But the sequence you are following for using self refresh is correct. You can verify this by leaving it on overnight and verifying the memory contents are still there, which is your main goal anyway.

    Jeff

  • 0 in reply to jc-ti
    Prodigy 220 points

    Hi Jeff,

    Thank you for your reply. I did run the self-refresh test overnight and the data was preserved. I also ran the power-down test for 3 hours and the data was also preserved.

    Here are the details of the power-down sequence:

    1. Write to DDR.

    2. Enable power-down
        a. Set the SR_PD bit (0x00800000 - bit 23) in SDRCR.
        b. Enable low-power mode by setting the LPMODEN bit (0x80000000 - bit 31) in SDRCR
        c. Enable MCLK stopping by setting the MCLKSTOPEN bit (0x40000000 - bit 30) in SDRCR.
        d. Delay for 150 clock cycles (using a delay timer for 1 mircosecond).

    3. Wait for 64 seconds (1000 times the refresh period.

    4. Diable power-down
        a. Set the RESET_PHY bit (0x00000400 - bit 10) in DRPYCR.
        b. Disable MCLK stopping by clearing the MCLKSTOPEN bit in SDRCR.
        c. Disable low-power mode by clearing the LPMODEN bit in SDRCR.

    5. Read from DDR.

    Prior to these steps, PSC is initialized, PLLs are configured, DDR is initialized, a timer is initialized, and a UART port is initialized for debug output. Let me know if you would like those details as well.

    I'm more confident about the self-refresh mode now, because I set the partial self-refresh array to 1 bank and the data that was not refreshed failed.

    Thanks,
    Wes