reference clock for ethernet on c6678?

Hi Yoonsun,

Yes, we have to configure the MPY and rate scale of SGMII SERDES PLL for your newer reference clock input.

If you look into "PA_multicoreExample_exampleProject" example code,

C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\PA_multicoreExample_exampleProject

You have to change the SGMII multiply value in the following file.

cpsw_mgmt.c

Int32 Init_SGMII_SERDES(Void)
{
/*
* The following SERDES configuration is required for chip simulator only.
* The platform-dependent SERDES configuration should be done by the corresponding
* CCS GEL scripts or platformLib
*/
if (cpswSimTest)
{
/* Unlock the chip configuration registers to allow SGMII SERDES registers to
* be written */
CSL_BootCfgUnlockKicker();

CSL_BootCfgSetSGMIIConfigPLL (0x00000041); // Need to modify the MPY field
CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621); // Need to modify RATE field
CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1); // Need to modify RATE
CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621); // Need to modify RATE
CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1); // Need to modify RATE

/* Re-lock the chip configuration registers to prevent unintentional writes */
CSL_BootCfgLockKicker();
}

/* SGMII SERDES Configuration complete. Return. */
return 0;
}


Please refer to the following document "sprugv9d" (chapter 3.6.2 and 3.6.3, 3.6.4) for further register changes.

www.ti.com/.../sprugv9d.pdf